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ds07-13608-1e fujitsu semiconductor data sheet 16-bit proprietary microcontroller cmos f 2 mc-16l mb90640a series MB90641A/p641a n description mb90640a series includes 16-bit microcontrollers optimally suitable for process control in a wide variety of industrial and oa equipment. the series uses the f 2 mc*-16l cpu which is based on the f 2 mc-16 but with enhanced high-level language and task switching instructions and additional addressing modes. the internal peripheral resources consist of a 2-channel serial port incorporating a uart function (and supporting i/o expansion serial mode), 8/16-bit 2-channel ppg, 5-channel 16-bit reload timer, 8-channel chip select function, and 8-channel dtp/external interrupts. also, multiplexed or non-multiplexed operation can be selected for the address/data bus. *: f 2 mc stands for fujitsu flexible microcontroller. n features f 2 mc-16l cpu ? minimum instruction execution time: 58.8 ns/4.25 mhz oscillation (uses pll clock multiplication), maximum multiplier = 4 ? instruction set optimized for controller applications upward object code compatibility with f 2 mc-16 (h) wide range of data types (bit/byte/word/long word) improved instruction cycles provide increased speed additional addressing modes: 23 modes (continued) n pac k ag e 100-pin plastic lqfp (fpt-100p-m05) 100-pin plastic qfp (fpt-100p-m06)
2 mb90640a series (continued) high code efficiency access methods (bank access/linear pointer) enhanced multiplication and division instructions (signed instructions added) high precision operations are enhanced by use of a 32-bit accumulator extended intelligent i/o service (access area extended to 64 kbytes) maximum memory space: 16 mbytes ? enhanced high level language (c)/multitasking support instructions use of a system stack pointer enhanced pointer indirect instructions barrel shift instructions stack check function ? improved execution speed: four byte instruction queue ? powerful interrupt function ? automatic data transfer function (does not use instructions) internal peripherals ? ram: 2 kbytes ? general purpose ports data bus, multiplexed mode: 56 ports max. non-multiplexed mode: 48 ports max. single-chip mode: 75 ports max. ? uart0, 1 (sci): 2 channels for either asynchronous or clocked serial transfer (i/o expansion serial) ? 8/16-bit ppg (programmable pulse generator): 2 channels ? 16-bit reload timer: 5 channels ? chip select function: 8 channels ? dtp/external interrupts: 8 channels ? timebase timer/watchdog timer ? pll clock multiplier function ? cpu intermittent operation function ? various standby modes ? packages: lqfp-100 and qfp-100 ? cmos technology
3 mb90640a series n product lineup MB90641A mb90p641a classification mask rom one-time prom rom size 64 kbytes 64 kbytes ram size 2 kbytes 2 kbytes cpu functions the number of instructions: 340 instruction bit length: 8/16 bits instruction length: 1 to 7 bytes data bit length: 1/4/8/16/32 bits minimum execution time: 58.8 ns at 4.25 mhz (pll multiplier = 4) interrupt processing time: 941 ns at 17 mhz (minimum) ports 8/16-bit data bus, multiplexed mode: 56 ports (max) 8-bit non-multiplexed mode: 48 ports (max) single-chip mode: 75 ports (max) packages fpt-100p-m05 fpt-100p-m06 uart0, 1 (sci) two internal uarts full-duplex, double-buffered selectable clock synchronous or asynchronous operation built-in dedicated baud rate generator 8/16-bit ppg 2 8-bit ppg outputs (1 channel ppg output in 16-bit mode) 16-bit reload timer 16-bit reload timer operation (selectable toggle output, one-shot output) (selectable count clock: 0.125 m s, 0.5 m s, or 2.0 m s for a 16 mhz machine cycle) selectable event count function, 5 internal channels chip select function 8 outputs dtp/external interrupts 8 inputs external interrupt mode (interrupts can be generated from four different types of request signal) pll function selectable multiplier: 1/2/3/4 (set a multiplier that does not exceed the assured operation frequency range.) external bus terminal control circuit multiplex and non-multiplex between the adress pin and the data pin is selectable. part number item
4 mb90640a series n pin assignment 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 rst p54/wrh p53/hrq p52/hak p51/rdy p50/clk pa7/cs7 pa6/cs6 pa5/cs5 pa4/cs4 pa3/cs3 pa2/cs2 pa1/cs1 pa0/cs0 p95 p94 p93 p92/sck1 p91/sot1 p90/sin1 p86/sck0 p85/sot0 p84/sin0 p83/tim3 p82/tim2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 p22/a02 p23/a03 p24/a04 p25/a05 p26/a06 p27/a07 p30/a08 p31/a09 v ss p32/a10 p33/a11 p34/a12 p35/a13 p36/a14 p37/a15 p40/a16 p41/a17 p42/a18 p43/a19 p44/a20 v cc p45/a21 p46/a22 p47/a23 c p71/int1 p72/int2 p76/int6 v cc v cc v ss v ss p60 p61 p62 p63 v ss p64 p65 p66 p67 md0 md1 md2 hst p73/int3/tim4 p74/int4/ppg0 p75/int5/ppg1 p80/int7/tim0 p81/int0/tim1 p21/a01 p20/a00 p17/d15/ad15 p16/d14/ad14 p15/d13/ad13 p14/d12/ad12 p13/d11/ad11 p12/d10/ad10 p11/d09/ad09 p10/d08/ad08 p07/d07/ad07 p06/d06/ad06 p05/d05/ad05 p04/d04/ad04 p03/d03/ad03 p02/d02/ad02 p01/d01/ad01 p00/d00/ad00 v cc x1 x0 v ss p57/ale p56/rd p55/wrl (top view) 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 (fpt-100p-m05)
5 mb90640a series 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 p57/ale p56/rd p55/wrl rst p54/wrh p53/hrq p52/hak p51/rdy p50/clk pa7/cs7 pa6/cs6 pa5/cs5 pa4/cs4 pa3/cs3 pa2/cs2 pa1/cs1 pa0/cs0 p95 p94 p93 p92/sck1 p91/sot1 p90/sin1 p86/sck0 p85/sot0 p84/sin0 p83/tim3 p82/tim2 hst md2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v ss p32/a10 p33/a11 p34/a12 p35/a13 p36/a14 p37/a15 p40/a16 p41/a17 p42/a18 p43/a19 p44/a20 v cc p45/a21 p46/a22 p47/a23 c p71/int1 p72/int2 p73/int3/tim4 p20/a00 p21/a01 p22/a02 p23/a03 p24/a04 p25/a05 p26/a06 p27/a07 p30/a08 p31/a09 p74/int4/ppg0 p75/int5/ppg1 p76/int6 v cc v cc v ss v ss p60 p61 p62 p63 v ss p64 p65 p66 p67 p80/int7/tim0 p81/int0/tim1 md0 md1 p04/d04/ad04 p03/d03/ad03 p02/d02/ad02 p01/d01/ad01 p00/d00/ad00 v cc x1 x0 v ss p17/d15/ad15 p16/d14/ad14 p15/d13/ad13 p14/d12/ad12 p13/d11/ad11 p12/d10/ad10 p11/d09/ad09 p10/d08/ad08 p07/d07/ad07 p06/d06/ad06 p05/d05/ad05 (top view) 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 (fpt-100p-m06)
6 mb90640a series n pin description (continued) *1: fpt-100p-m05 *2: fpt-100p-m06 pin no. pin name circuit type function lqfp* 1 qfp* 2 80, 81 82, 83 x0, x1 a crystal oscillator pins 47 to 49 49 to 51 md0 to md2 e (cmos) input pins for specifying an opration mode. use these pins by directly connecting v cc or v ss . 75 77 rst g (cmos/h) external reset request input pin 50 52 hst f (cmos/h) hardware standby input pin 83 to 90 85 to 92 p00 to p07 j (ttl) general purpose i/o ports this applies in single-chip mode with an external data bus in 8-bit mode. d00 to d07 in non-multiplex mode, the i/o pins for the lower 8 bits of the external data bus. ad00 to ad07 in multiplexed mode, the i/o pins for the lower 8 bits of the external address/data bus. 91 to 98 93 to 100 p10 to p17 j (ttl) general purpose i/o ports this applies in non-multiplexed mode with an 8-bit external data bus and in single-chip mode. p08 to d15 in non-multiplexed mode with a 16-bit external data bus, the i/o pins for the upper 8 bits of the external data bus. ad08 to ad15 in multiplexed mode, the i/o pins for the upper 8 bits of the external address/data bus. 99, 100, 1 to 6 1, 2, 3 to 8 p20, p21, p22 to p27 b (cmos) general purpose i/o ports this applies in multiplexed mode. a00, a01, a02 to a07 in non-multiplexed mode, the output pins for the lower 8 bits of the external address bus. 7, 8, 10 to 15 9, 10, 12 to 17 p30, p31, p32 to p37 b (cmos) general purpose i/o ports this applies in multiplexed mode. a08, a09, a10 to a15 in non-multiplexed mode, the output pins for the upper 8 bits of the external address bus. 16 to 20, 22 to 24 18 to 22, 24 to 26 p40 to p44, p45 to p47 b (cmos) general purpose i/o ports this applies when the upper address control register specifies port operation. a16 to a20, a21 to a23 output pins for a16 to a23 of the external address bus this applies when the upper address control register specifies address operation.
7 mb90640a series (continued) *1: fpt-100p-m05 *2: fpt-100p-m06 pin no. pin name circuit type function lqfp* 1 qfp* 2 70 72 p50 i (cmos) general purpose i/o port this applies when clk output is disabled. clk clk output pin this applies when clk output is enabled. 71 73 p51 k (ttl) general purpose i/o port this applies when the external ready function is disabled. rdy ready input pin this applies when the external ready function is enabled. 72 74 p52 i (cmos) general purpose i/o port this applies when the hold function is disabled. hak hold acknowledge output pin this applies when the hold function is enabled. 73 75 p53 k (ttl) general purpose i/o port this applies when the hold function is disabled. hrq hold request input pin this applies when the hold function is enabled. 74 76 p54 i (cmos) general purpose i/o port this applies in 8-bit external bus mode or when output is disabled for the wrh pin. wrh write strobe output pin for the upper 8 bits of the data bus this applies in 16-bit external bus mode and when output is enabled for the wrh pin. 76 78 p55 i (cmos) general purpose i/o port this applies when output is disabled for the wrl pin. wrl write strobe output pin for the lower 8 bits of the data bus this applies when output is enabled for the wrl pin. 77 79 p56 i (cmos) general-purpose i/o port this port is available in the single-chip mode. rd read strobe output pin for the data bus 78 80 p57 i (cmos) general-purpose i/o port this port is available in the single-chip mode. ale address latch enable output pin 36 to 39, 41 to 44 38 to 41, 43 to 46 p60 to p67 c open-drain output ports
8 mb90640a series (continued) *1: fpt-100p-m05 *2: fpt-100p-m06 pin no. pin name circuit type function lqfp* 1 qfp* 2 26, 27 28, 29 p71, p72 h (cmos/h) general purpose i/o ports this applies in all cases. int1, int2 external interrupt request input pins as the inputs operate continuously when external interrupts are enabled, output to the pins from other functions must be stopped unless done intentionally. 28 30 p73 h (cmos/h) general purpose i/o ports this applies when output is disabled for reload timers. int3 external interrupt request input pins as the inputs operate continuously when external interrupts are enabled, output to the pins from other functions must be stopped unless done intentionally. tim4 i/o pins for reload timers input is used only as necessary while serving as input for the reload timer. it is therefore necessary to stop output beforehand using other functions unless intentionally used otherwise. their function as output terminals for the reload timer is activated when the output specification is enabled. 29, 30 31, 32 p74, p75 h (cmos/h) general purpose i/o ports this applies when the waveform outputs for ppg timers 0, 1 are disabled. int4, int5 external interrupt request input pin as the input operates continuously when the external interrupt is enabled, output to the pin from other functions must be stopped unless done intentionally. ppg0, ppg1 output pins for ppg timers this applies when the waveform outputs for ppg timers 0, 1 are enabled. 31 33 p76 h (cmos/h) general purpose i/o port this applies in all cases. int6 external interrupt request input pin as the input operates continuously when the external interrupt is enabled, output to the pin from other functions must be stopped unless done intentionally.
9 mb90640a series (continued) *1: fpt-100p-m05 *2: fpt-100p-m06 pin no. pin name circuit type function lqfp* 1 qfp* 2 45, 46 47, 48 p80, p81 h (cmos/h) general purpose i/o ports this applies when output is disabled for reload timers. int7, int0 external interrupt request input pin as the input operates continuously when the external interrupt is enabled, output to the pin from other functions must be stopped unless done intentionally. tim0, tim1 i/o pins for reload timers input is used only as necessary while serving as input for the reload timer. it is therefore necessary to stop output beforehand using other functions unless intentionally used otherwise. their function as output terminals for the reload timer is activated when the output specification is enabled. 51, 52 53, 54 p82, p83 d (cmos/h) general purpose i/o ports this applies when output is disabled for reload timers. tim2, tim3 i/o pins for reload timers input is used only as necessary while serving as input for the reload timer. it is therefore necessary to stop output beforehand using other functions unless intentionally used otherwise. their function as output terminals for the reload timer is activated when the output specification is enabled. 53 55 p84 d (cmos/h) general purpose i/o port this applies in all cases. sin0 serial data input pin for uart0 as the input operates continuously when uart0 is set to input operation, output to the pin from other functions must be stopped unless done intentionally. 54 56 p85 d (cmos/h) general purpose i/o port this applies when serial data output is disabled for uart0. sot0 serial data output pin for uart0 this applies when serial data output is enabled for uart0. 55 57 p86 d (cmos/h) general purpose i/o port this applies when the uart0 clock output is disabled. sck0 clock i/o pin for uart0 this applies when the uart0 clock output is enabled. as the input operates continuously when uart0 is set to input operation, output to the pin from other functions must be stopped unless done intentionally. 56 58 p90 d (cmos/h) general purpose i/o port this applies in all cases. sin1 serial data input pin for uart1 as the input operates continuously when uart1 is set to input operation, output to the pin from other functions must be stopped unless done intentionally.
10 mb90640a series (continued) *1: fpt-100p-m05 *2: fpt-100p-m06 pin no. pin name circuit type function lqfp* 1 qfp* 2 57 59 p91 d (cmos/h) general purpose i/o port this applies when serial data output is disabled for uart1. sot1 serial data output pin for uart1 this applies when serial data output is enabled for uart1. 58 60 p92 d (cmos/h) general purpose i/o port this applies when the uart1 clock output is disabled. sck1 clock i/o pin for uart1 this applies when the uart1 clock output is enabled. as the input operates continuously when uart1 is set to input operation, output to the pin from other functions must be stopped unless done intentionally. 59 to 61 61 to 63 p93 to p95 d (cmos/h) general purpose i/o port 25 27 c capacitor pin for stabilizing power supply connect about 0.1 m f ceramic capacitor outside rom. mb90p641 doesnt need to be connected the capacitor. it isnt problem even the capacitor is connected to mb90p641a. 62 to 69 64 to 71 pa0 to pa7 i (cmos/h) general purpose i/o ports this applies for pins with chip select output disabled by the chip select control register. cs0 to cs7 output pins for the chip select function this applies for pins with chip select output enabled by the chip select control register. 21, 32, 33, 82 23, 34, 35, 84 v cc power supply power supply for the digital circuits 9, 34, 35, 40, 79 11, 36, 37, 42, 81 v ss power supply ground level for the digital circuits
11 mb90640a series n i/o circuit type note: for pins with pull-up resistors, the resistance is disconnected when the pin outputs the l level or when in the standby state. (continued) type circuit remarks a ? max. 3 to 34 mhz ? oscillation feedback resistance:approximately 1 m w b ? cmos level i/o with standby control ? pull-up resistor option c ? n-channel open-drain output ? cmos level hysteresis input ? pull-up resistor option d ? cmos level output ? cmos level hysteresis input with standby control ? pull-up resistor option x1 x0 standby control clock input standby control digital input digital output digital output r standby control digital input digital output r standby control digital input digital output digital output r
12 mb90640a series note: for pins with pull-up resistors, the resistance is disconnected when the pin outputs the l level or when in the standby state. (continued) type circuit remarks e ? cmos level input no standby control ? pull-up resistor option f ? cmos level hysteresis input no standby control ? pull-up resistor option g ? cmos level hysteresis input no standby control ? with pull-up resistor h ? cmos level output ? cmos level hysteresis input no standby control ? pull-up resistor option i ? cmos level output ? cmos level hysteresis input ? pull-up resistor approximately 50 k w ? pin goes to high impedance during stop mode. digital input r digital input r digital input r r digital output digital output digital input r standby control digital input digital output digital output r r standby control
13 mb90640a series (continued) note: for pins with pull-up resistors, the resistance is disconnected when the pin outputs the l level or when in the standby state. type circuit remarks j ? cmos level output ? ttl level input with standby control ? pull-up resistor option k ? cmos level output ? ttl level input ? pull-up resistor approximately 50 k w ? pin goes to high impedance during stop mode. standby control digital input digital output digital output r standby control digital input digital output digital output r standby control r
14 mb90640a series n handling devices 1. preventing latchup latchup may occur on cmos ics if voltage higher than v cc or less than v ss is applied to input and output pins other than medium- and high-voltage pins or if higher than the voltage which shows on 1. absolute maximum ratings in n electrical characteristics is applied between v cc and v ss . when latchup occurs, power supply current increases rapidlly and might thermally damage elements. when using, take great care not to exceed the absolute maximum ratings. also, take care to prevent the anaolg power supply (av cc and avr) and analog input from exceeding the digital power supply (v cc ) when the analog system power supply is truned on and off. 2. treatment of unused pins leaving unused input pins open could cause malfunctions. they should be connected to a pull-up or pull-down resister. 3. cautions when using an external clock drive the x0 pin only when using an external clock. 4. power supply pins when there are several v cc and v ss pins, those pins that should have the same electric potential are connected within the device when the device is designed in order to prevent misoperation, such as latchup. however, all of those pins must be connected to the power supply and ground externally in order to reduce unnecessary emissions, prevent misoperation of strobe signals due to an increase in the ground level, and to observe the total output current standards. in addition, give a due consideration to the connection in that current supply be connected to v cc and v ss with the lowest possible impedance. finally, it is recommended to connect a ceramic capacitor of about 0.1 m f between v cc and v ss near this device as a bypass capacitor. 5. crystal oscillation circuit noise in the vicinity of the x0 and x1 pins will cause this device to operate incorrectly. design the printed circuit board so that the bypass capacitor connecting x0, x1 and the crystal oscillator (or ceramic oscillator) to ground is located as close to the device as possible, and possibly take care not to cross over the other wiring with this wiring. in addition, because printed circuit board artwork in which the area around the x0 and x1 pins is surrounded by ground provides stable operation, such an arrangement is strongly recommended. x0 x1 mb90640a open ? using an external clock
15 mb90640a series n programming to the one-time prom on the mb90p641a mb90p641a has a function prom mode function equivalent to mbm27c1000/1000a, so it can be written by general rom writer using special adapter. but take attention it doesnt corsespond to the elctronic signature (the device identification code) mode. 1. programming procedure memory map in the prom mode is as below. write option data to the option setting erea refering to the 6 prom option bit map. porocedure of the programing to the one-time prom microcomputer is as below. (1) set the eprom programmer for the mbm27c1000/1000a. (2) load the program data into the eprom programmer at address* 1 to 1ffff h . when specify the prom option, load the option data to 00000 h to 00002c h to refering to 6. prom option bitmap. (3) insert the device in the socket adapter, and mount the socket adapter on the eprom programmer. pay attention to the orientation of the device and of the socket adapter when doing so. (4) program to 00000 h to 1ffff h. notes: ? because the mask rom products do not have a prom mode, they cannot read date from the eprom programmer. ? contact the sales department when purchasing an eprom programmer. note: the 00 bank rom image is 48 kbyes. (this is a rom image for ff4000 h to ffffff h . only when the rom mirror function selecting resister is enable.) product address *1 address *2 number of bytes mb90p641a 10000 h ff0000 h 64 kbytes normal operating made ffffff h 010000 h 004000 h 000000 h address* 2 program area (prom) 1ffff h 0002c h rom image 00000 h address* 1 program area (prom) prom mode mirror option setting area
16 mb90640a series 2. program mode in the mb90p641a, all of the bits are set to 1 when the ic is shipped from fujitsu and after erasure. to input data, program the ic by selectively setting the desired bits to 0. bits cannot be set to 1 electrically. 3. recommended screening conditions high-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked one-time prom with microcontroller program. 4. programming yield all bits cannot be programmed at fujitsu shipping test to a blanked one-time prom microcomputer, due to its nature. for this reason, a programming yield of 100% cannot be assured at all times. 5. eprom programmer socket adapter and recommended programmer manuffacturer inquiry: sun hayato co., ltd.: tel: (81)-3-3986-0403 fax: (81)-3-5396-9106 minato electronics inc.: tel: usa (1)-916-348-6066 japan (81)-45-591-5611 part no. mb90p641apf mb90p641apfv package qfp-100 lqfp-100 compatible socket adapter sun hayato co., ltd. rom-100qf-32dp -ffmc-16l rom-100sqf-32dp -ffmc-16l recommended programmer manufacturer and programmer name minato electronics inc. 1890a recommended recommended 1891 recommended recommended 1930 recommended recommended assembly program, verify aging +150 c, 48 hrs. data verification
17 mb90640a series 6. prom option bitmap note: write data 1 to the vacant bit and the adress other than above. address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00000 h vacancy rst pull-up 1: no 0: yes vacancy md 1 pull-up 1: no 0: yes md 1 pull-down 1: no 0: yes md 0 pull-up 1: no 0: yes md 0 pull-down 1: no 0: yes vacancy 00004 h p07 pull-up 1: no 0: yes p06 pull-up 1: no 0: yes p05 pull-up 1: no 0: yes p04 pull-up 1: no 0: yes p03 pull-up 1: no 0: yes p02 pull-up 1: no 0: yes p01 pull-up 1: no 0: yes p00 pull-up 1: no 0: yes 00008 h p17 pull-up 1: no 0: yes p16 pull-up 1: no 0: yes p15 pull-up 1: no 0: yes p14 pull-up 1: no 0: yes p13 pull-up 1: no 0: yes p12 pull-up 1: no 0: yes p11 pull-up 1: no 0: yes p10 pull-up 1: no 0: yes 0000c h p27 pull-up 1: no 0: yes p26 pull-up 1: no 0: yes p25 pull-up 1: no 0: yes p24 pull-up 1: no 0: yes p23 pull-up 1: no 0: yes p22 pull-up 1: no 0: yes p21 pull-up 1: no 0: yes p20 pull-up 1: no 0: yes 00010 h p37 pull-up 1: no 0: yes p36 pull-up 1: no 0: yes p35 pull-up 1: no 0: yes p34 pull-up 1: no 0: yes p33 pull-up 1: no 0: yes p32 pull-up 1: no 0: yes p31 pull-up 1: no 0: yes p30 pull-up 1: no 0: yes 00014 h p47 pull-up 1: no 0: yes p46 pull-up 1: no 0: yes p45 pull-up 1: no 0: yes p44 pull-up 1: no 0: yes p43 pull-up 1: no 0: yes p42 pull-up 1: no 0: yes p41 pull-up 1: no 0: yes p40 pull-up 1: no 0: yes 0001c h p57 pull-up 1: no 0: yes p56 pull-up 1: no 0: yes p55 pull-up 1: no 0: yes p54 pull-up 1: no 0: yes p53 pull-up 1: no 0: yes p52 pull-up 1: no 0: yes p51 pull-up 1: no 0: yes p50 pull-up 1: no 0: yes 00020 h vacancy p76 pull-up 1: no 0: yes p75 pull-up 1: no 0: yes p74 pull-up 1: no 0: yes p73 pull-up 1: no 0: yes p72 pull-up 1: no 0: yes p71 pull-up 1: no 0: yes vacancy 00024 h vacancy p86 pull-up 1: no 0: yes p85 pull-up 1: no 0: yes p84 pull-up 1: no 0: yes p83 pull-up 1: no 0: yes p82 pull-up 1: no 0: yes p81 pull-up 1: no 0: yes p80 pull-up 1: no 0: yes 00028 h vacancy vacancy p95 pull-up 1: no 0: yes p94 pull-up 1: no 0: yes p93 pull-up 1: no 0: yes p92 pull-up 1: no 0: yes p91 pull-up 1: no 0: yes p90 pull-up 1: no 0: yes 0002c h pa 7 pull-up 1: no 0: yes pa 6 pull-up 1: no 0: yes pa 5 pull-up 1: no 0: yes pa 4 pull-up 1: no 0: yes pa 3 pull-up 1: no 0: yes pa 2 pull-up 1: no 0: yes pa 1 pull-up 1: no 0: yes pa 0 pull-up 1: no 0: yes
18 mb90640a series n block diagram clock control circuit ram interrupt controller 8 8 8 8 8 8 67 p10 to p17 p20 to p27 p30 to p37 p40 to p47 p50 to p57 p60 to p67 p71 to p76 p80 to p86 i/o ports cpu f 2 mc-16l family core rom dtp/external interrupts 6 p90 to p95 8 8 int0 to int7 8 pa0 to pa7 x0, x1 rst hst md0 to md2 16-bit reload timer chip select functions cs0 to cs7 tim0 to tim4 8/16-bit ppg 8 p00 to p07 uart external bus interface sin0, sin1 sot0, sot1 sck0, sck1 communication prescaler ppg0 ppg1 a00 to a23 d00 to d15 ale rd wrl, wrh hrq hak rdy clk internal data bus (output switching) 1channel 7 2 2 2 16 2 5 24 ohter pins ad00 to ad15, c, v cc , v ss
19 mb90640a series n memory map ffffff h ff0000 h f00000 h 00ffff h 004000 h 002000 h 000100 h 000000 h 0000c0 h address #1 single chip mode internal rom/ external bus mode external rom/ external bus mode rom area rom area (ff bank image) ram registers peripherals rom area rom area (ff bank image) ram registers peripherals ram registers peripherals : internal access memory : external access memory : no access MB90641A mb90p641a 000900 h 000900 h type address #1 note: when disable output upper address a23 to a16 of mb90640a series, the maximum acceptable size becomes 64 kbytes.
20 mb90640a series n f 2 mc-16l cpu programming model ah al dpr pcb dtb usb ssb adb 8 bits 16 bits 32 bits accumulator usp ssp ps pc user stack pointer system stack pointer processor status program counter direct page register program bank register data bank register user stack bank register system stack bank register additional data bank register 32 banks (max.) r7 r6 r5 r4 r3 r2 r1 r0 rw3 rw2 rw1 rw0 16 bits 000180 h + rp 10 h ? rw7 rw6 rw5 rw4 rl3 rl2 rl1 rl0 ilm rp i s t n z v c ccr ? dedicated registers ? processor status (ps) ? general-purpose registers
21 mb90640a series n i/o map (continued) address name register read/ write* 4, * 5 resource name initial value 000000 h pdr0 port 0 data register r/w* por t 0 *8 xxxxxxxx b 000001 h pdr1 port 1 data register r/w* por t 1 *7 xxxxxxxx b 000002 h pdr2 port 2 data register r/w* por t 2 *6 xxxxxxxx b 000003 h pdr3 port 3 data register r/w* por t 3 *6 xxxxxxxx b 000004 h pdr4 port 4 data register r/w port 4 xxxxxxxx b 000005 h pdr5 port 5 data register r/w por t 5 *8 xxxxxxxx b 000006 h pdr6 port 6 data register r/w port 6 11111111 b 000007 h pdr7 port 7 data register r/w port 7 Cxxxxxxx b 000008 h pdr8 port 8 data register r/w port 8 Cxxxxxxx b 000009 h pdr9 port 9 data register r/w port 9 C Cxxxxxx b 00000a h pdra port a data register r/w por t a *8 xxxxxxxC b 00000b h to 0f h vacancy *3 000010 h ddr0 port 0 direction register r/w* por t 0 *8 00000000 b 000011 h ddr1 port 1 direction register r/w* por t 1 *7 00000000 b 000012 h ddr2 port 2 direction register r/w* por t 2 *6 00000000 b 000013 h ddr3 port 3 direction register r/w* por t 3 *6 00000000 b 000014 h ddr4 port 4 direction register r/w port 4 00000000 b 000015 h ddr5 port 5 direction register r/w por t 5 *8 00000000 b 000016 h ddr6 port 6 direction register r/w port 6 11111111 b 000017 h ddr7 port 7 direction register r/w port 7 C000000C b 000018 h ddr8 port 8 direction register r/w port 8 C0000000 b 000019 h ddr9 port 9 direction register r/w port 9 CC000000 b 00001a h ddra port a direction register r/w por t a *8 00000000 b 00001b h to 1f h vacancy *3 000020 h smr0 serial mode register 0 r/w! uart0 (sci) 00000000 b 000021 h scr0 serial control register 0 r/w! 00000100 b 000022 h sidr0/ sodr0 input data register 0/ output data register 0 r/w xxxxxxxx b 000023 h ssr0 serial status register 0 r/w! 00001C00 b 000024 h smr1 serial mode register 1 r/w! uart1 (sci) 00000000 b 000025 h scr1 serial control register 1 r/w! 00000100 b 000026 h sidr1/ sodr1 input data register 1/ output data register 1 r/w xxxxxxxx b 000027 h ssr1 serial status register 1 r/w! 00001C00 b
22 mb90640a series (continued) address name register read/ write* 4, * 5 resource name initial value 000028 h enir interrupt/dtp enable register r/w dtp/external interrupt 00000000 b 000029 h eirr interrupt/dtp request register r/w xxxxxxxx b 00002a h elvr interrupt level setting register r/w 00000000 b 00002b h 00000000 b 00002c h to 2f h vacancy *3 000030 h ppgc0 ppg0 operation mode control register r/w 8/16-bit ppg0 0C000001 b 000031 h ppgc1 ppg1 operation mode control register r/w 8/16-bit ppg1 00000001 b 000032 h , 33 h vacancy *3 000034 h prll0/ prlh0 ppg0 reload register r/w 8/16-bit ppg0 xxxxxxxx b 000035 h xxxxxxxx b 000036 h prll1/ prlh1 ppg1 reload register r/w 8/16-bit ppg1 xxxxxxxx b 000037 h xxxxxxxx b 000038 h tmcsr0 timer control status register r/w! 16-bit reload timer 0 00000000 b 000039 h CCCC0000 b 00003a h tmr0/ tmrlr0 16-bit timer register/ 16-bit reload register r/w xxxxxxxx b 00003b h xxxxxxxx b 00003c h tmcsr1 timer control status register r/w! 16-bit reload timer 1 00000000 b 00003d h CCCC0000 b 00003e h tmr1/ tmrlr1 16-bit timer register/ 16-bit reload register r/w xxxxxxxx b 00003f h xxxxxxxx b 000040 h to 47 h vacancy *3 000048 h cscr0 chip select control register 0 r/w chip select function CCCC0000 b 000049 h cscr1 chip select control register 1 r/w CCCC0000 b 00004a h cscr2 chip select control register 2 r/w CCCC0000 b 00004b h cscr3 chip select control register 3 r/w CCCC0000 b 00004c h cscr4 chip select control register 4 r/w CCCC0000 b 00004d h cscr5 chip select control register 5 r/w CCCC0000 b 00004e h cscr6 chip select control register 6 r/w CCCC0000 b 00004f h cscr7 chip select control register 7 r/w CCCC0000 b 000050 h vacancy *3 000051 h cdcr0 uart0 (sci) machine clock division control register w uart0 (sci) CCCC1111 b
23 mb90640a series (continued) address name register read/ write* 4, * 5 resource name initial value 000052 h vacancy *3 000053 h cdcr1 uart1 (sci) machine clock division control register w uart1 (sci) CCCC1111 b 000054 h to 57 h vacancy *3 000058 h tmcsr2 timer control status register r/w! 16-bit reload timer 2 00000000 b 000059 h CCCC0000 b 00005a h tmr2/ tmrlr2 16-bit timer register/ 16-bit reload register r/w xxxxxxxx b 00005b h xxxxxxxx b 00005c h tmcsr3 timer control status register r/w! 16-bit reload timer 3 00000000 b 00005d h CCCC0000 b 00005e h tmr3/ tmrlr3 16-bit timer register/ 16-bit reload register r/w xxxxxxxx b 00005f h xxxxxxxx b 000060 h tmcsr4 timer control status register r/w! 16-bit reload timer 4 00000000 b 000061 h CCCC0000 b 000062 h tmr4/ tmrlr4 16-bit timer register/ 16-bit reload register r/w xxxxxxxx b 000063 h xxxxxxxx b 000064 h tpcr timer pin control register r/w 16-bit reload timer 00010000 b 000065 h 00110010 b 000066 h CCCC0100 b 000067 h to 6e h vacancy *3 00006f h romm rom mirror functional selection module w rom mirror function *9 CCCCCCC* b 000070 h to 8f h vacancy *3 000090 h to 9e h reserved system area *1 00009f h dirr delayed interrupt generation/ release register r/w delayed interrupt generation module CCCCCCC0 b 0000a0 h lpmcr low power consumption mode control register r/w! low power consumption controller circuits 00011000 b 0000a1 h ckscr clock selection register r/w! 11111100 b 0000a2 h to a4 h vacancy *3 0000a5 h arsr auto-ready function selection register w external bus pin controller circuits 0011CC00 b
24 mb90640a series (continued) initial values 0: the initial value for this bit is 0. 1: the initial value for this bit is 1. *: the initial value for this bit is 1 or 0. (determined by the level of the md0 to md2 pins.) x: the initial value for this bit is undefined. C: this bit is not used. the initial value is undefined. *1: access prohibited. *2: this is the only external access area in the area below address 0000ff h . access this address as an external i/o area. *3: areas marked as vacancy in the i/o map are reserved areas. these areas are accessed by internal access. no access signals are output on the external bus. *4: the r/w! symbol in the read/write column indicates that some bits are read-only or write-only. see the resources register list for details. (continued) address name register read/ write* 4, * 5 resource name initial value 0000a6 h hacr external address output control register w external bus pin controller circuits 00000000 b 0000a7 h ecsr bus control signal selection register w C 0 0 * 0 0 0 0 b 0000a8 h wdtc watchdog timer control register r/w! watchdog timer xxxxx11 1 b 0000a9 h tbtc timebase timer control register r/w! timebase timer 1CC00100 b 0000aa h to af h vacancy *3 0000b0 h icr00 interrupt control register 00 r/w! interrupt controller 00000111 b 0000b1 h icr01 interrupt control register 01 r/w! 00000111 b 0000b2 h icr02 interrupt control register 02 r/w! 00000111 b 0000b3 h icr03 interrupt control register 03 r/w! 00000111 b 0000b4 h icr04 interrupt control register 04 r/w! 00000111 b 0000b5 h icr05 interrupt control register 05 r/w! 00000111 b 0000b6 h icr06 interrupt control register 06 r/w! 00000111 b 0000b7 h icr07 interrupt control register 07 r/w! 00000111 b 0000b8 h icr08 interrupt control register 08 r/w! 00000111 b 0000b9 h icr09 interrupt control register 09 r/w! 00000111 b 0000ba h vacancy *3 0000bb h icr11 interrupt control register 11 r/w! 00000111 b 0000bc h vacancy *3 0000bd h icr13 interrupt control register 13 r/w! 00000111 b 0000be h icr14 interrupt control register 14 r/w! 00000111 b 0000bf h icr15 interrupt control register 15 r/w! 00000111 b 0000c0 h to ff h (external area) *2
25 mb90640a series (continued) *5: using a read-modify-write instruction (such as the bit set instruction) to access one of the registers indicated by r/w!, r/w*, or w in the read/write column sets the specified bit to the desired value. however, this can cause misoperation if the other register bits include write-only bits. therefore, do not use read-modify-write instructions to access these registers. *6: this register is only available when the address/data bus is in multiplex mode and in single-chip mode. access to the register is prohibited in non-multiplex mode. *7: this register is only available when the external data bus is in 8-bit mode and in single-chip mode. access to the register is prohibited in 16-bit mode. *8: all bits of ddr0/pdr0, 6-bit/7-bit of ddr5/pdr5 and 0-bit of ddra/pdra are available only in single-chip mode. *9: the initial value of this register in mb90v640a is 0 and that of in mb90p641a, MB90641A is 1. note: the initial values listed for write-only bits are the initial values set by a reset. take attention that they are not the values returned by a read. also, lpmcr/ckscr/wdtc are sometimes initialized and sometimes not initialized, depending on the reset type. the listed initial values are for when these registers are initialized.
26 mb90640a series n interrupt vector and interrupt control register assignments to interrupt sources : indicates that the interrupt request flag is cleared by the i 2 os interrupt clear signal (no stop request). : indicates that the interrupt request flag is cleared by the i 2 os interrupt clear signal (with stop request). : indicates that the interrupt request flag is not cleared by the i 2 os interrupt clear signal. note: do not specify i 2 os activation in interrupt control registers that do not support i 2 os. interrupt source i 2 os support interrupt vector interrupt control register number address icr address reset #08 08 h ffffdc h int 9 instruction #09 09 h ffffd8 h exception #10 0a h ffffd4 h dtp/external interrupt #0 #11 0b h ffffd0 h icr00 0000b0 h dtp/external interrupt #1 #13 0d h ffffc8 h icr01 0000b1 h dtp/external interrupt #2 #15 0f h ffffc0 h icr02 0000b2 h dtp/external interrupt #3 #17 11 h ffffb8 h icr03 0000b3 h 16-bit reload timer #2 #18 12 h ffffb4 h dtp/external interrupt #4 #19 13 h ffffb0 h icr04 0000b4 h 16-bit reload timer #3 #20 14 h ffffac h dtp/external interrupt #5 #21 15 h ffffa8 h icr05 0000b5 h 16-bit reload timer #4 #22 16 h ffffa4 h dtp/external interrupt #6 #23 17 h ffffa0 h icr06 0000b6 h uart0 ? send complete #24 18 h ffff9c h dtp/external interrupt #7 #25 19 h ffff98 h icr07 0000b7 h uart1 ? send complete #26 1a h ffff94 h 8/16-bit ppg #0 #27 1b h ffff90 h icr08 0000b8 h 8/16-bit ppg #1 #28 1c h ffff8c h 16-bit reload timer #0 #29 1d h ffff88 h icr09 0000b9 h 16-bit reload timer #1 #30 1e h ffff84 h vacancy #31 1f h ffff80 h icr10 0000ba h timebase timer interval interrupt #34 22 h ffff74 h icr11 0000bb h vacancy #35 23 h ffff70 h icr12 0000bc h uart1 ? receive complete #37 25 h ffff68 h icr13 0000bd h uart0 ? receive complete #39 27 h ffff60 h icr14 0000be h delayed interrupt generation module #42 2a h ffff54 h icr15 0000bf h
27 mb90640a series n peripheral resources 1. parallel port the mb90640a series has 75 i/o pins, and 8 open-drain output pins. ports 0 to 5 and ports 7 to 9 and a are i/o ports. the ports are inputs when the corresponding direction register bit is 0 and outputs when the corresponding bit is 1. port 0 is only available in single-chip mode. port 1 is only available when in data bus 8-bit mode of non-multiplex mode or in single-chip mode. ports 2 and 3 are only available when the address/data bus is in multiplex mode and single-chip mode. port 6 is an open-drain port. (1) register details ? port data registers note: no register bit is provided for bits 0, 7 of port 7. no register bit is provided for bit 7 of port 8. no register bits are provided for bits 7, 6 of port 9. port 0 is only available in single-chip mode. bits 7, 6 of port 5 and bit 0 of port a are only available in single-chip mode. port 1 is only available when the external data bus is in 8-bit mode and single-chip mode. ports 2, 3 are only available in multiplex mode and single-chip mode. each port pin except port 6 can be specified as either an input or output by its corresponding direction register when the pin is not set for use by a peripheral. when a port is set as an input, reading the data register always reads the value corresponding to the pin level. when a port is set as an output, reading the data register reads the data register latch value. the same applies when reading using a read-modify-write instruction. when used as control outputs, reading the data register reads the control output value, irrespective of the direction register value. address : pdr1 pdr3 pdr5 pdr7 pdr9 pdr0 pdr2 pdr4 pdr6 pdr8 pdra pdx7 pdx6 pdx5 pdx4 pdx3 pdx2 pdx1 pdx0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w r/w r/w r/w r/w r/w r/w r/w initial value : 000001 h : 000003 h : 000005 h : 000007 h : 000009 h : 000000 h : 000002 h : 000004 h : 000006 h : 000008 h : 00000a h xxxxxxxx b address : pdx7 pdx6 pdx5 pdx4 pdx3 pdx2 pdx1 pdx0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w initial value xxxxxxxx b r/w x : readable and writable : indeterminate ? port data register
28 mb90640a series notes: ? if read-modify-write instructions (bit set instruction, etc.) are used to access this register, the bit that is the focus of the instruction is set to the prescribed value, but the contents of the output register corresponding to any other bits for which the input setting has been made are overwritten with the current input value of the corresponding pin. therefore, when switching a pin that was being used for input over to output, first write the desired value to pdr, and then set the data ddr as output direction. ? reading and writing an i/o port differs from reading and writing memory as follows: input mode reads: the read data is the level of the corresponding pin. writes: the write data is stored in the output latch. the data is not output to the pin. output mode reads: the read data is the value stored in the pdr. writes: the write data is both stored in the output latch and output to the pin. ? take attention that the operation of r/w in port 6 is different from that of in other port. port 6 (p67 to p60) is an general-purpose i/o port with an open-drain output. when port 6 is used as a general- purpose port, always be sure to set the corresponding bits in ddr6 to 0. when port 6 is used as an input port, it is necessary set the output port data register value to 1 in order to turn off the open-drain output transistor; it is also necessary to connect a pull-up resistor to the external pins. in addition, depending on the instruction used to read these bits, one of the following two different operations is performed: ? when read by a read-modify-write instruction: the contents of the output port data register are read. even if pins are forcibly set to 0 externally, the contents of the bits not specified by the instruction do not change. ? when read by any other instruction: the pin level can be read. when used as output ports, the pin values can be changed by writing the desired value to the corresponding output port data register. in addition, the pin which corresponds to the bit of which port 6 direction register is set to 1 can be read 0. ? port direction registers ddx7 ddx6 ddx5 ddx4 ddx3 ddx2 ddx1 ddx0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w r/w r/w r/w r/w r/w r/w r/w initial value : 000011 h : 000013 h : 000015 h : 000017 h : 000019 h : 000010 h : 000012 h : 000014 h : 000018 h : 00001a h 00000000 b address : ddx7 ddx6 ddx5 ddx4 ddx3 ddx2 ddx1 ddx0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000 b r/w : readable and writable address : ddr1 ddr3 ddr5 ddr7 ddr9 ddr0 ddr2 ddr4 ddr8 ddra ? port direction register
29 mb90640a series note: no register bit is provided for bits 0, 7 of port 7. no register bit is provided for bit 7 of port 8. no register bits are provided for bits 6, 7 of port 9. port 1 is only available in single-chip mode. port 1 is only available when the external data bus is in 8-bit mode and single-chip mode. ports 2, 3 are only available in multiplex mode and single-chip mode. when pins are used as ports, the register bits control the corresponding pins as follows. 0: input mode 1: output mode bits are set to 0 by a reset. ? port 6 direction register controls each pin of port 6 as follows. 0: port input mode 1: analog input mode bits are set to 1 by a reset. dd67 dd66 dd65 dd64 dd63 dd62 dd61 dd60 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w r/w r/w r/w r/w r/w r/w r/w initial value : 000016 h 11111111 b r/w: readable and writable address : ddr6 ? port 6 direction register
30 mb90640a series (2) block diagrams data register direction register data register read data register write direction register write direction register read pin data register ddr6 data register read data register write ddr6 register write ddr6 register read pin rmw (read-modify-write instruction) internal data bus internal data bus ? i/o port ? open-drain port
31 mb90640a series (3) port pin allocation ports 1, 4, and 5 on the mb90640a series share pins with the external bus. the pin functions are determined by the bus mode and register settings. notes: ? the upper address, wrl , wrh , hak , hrq, rdy, and clk can be set for use as ports by function selection. ? the pins mentioned above can be used as a port in single-chip mode. pin name function non-multiplex mode multiplex mode external address control external address control enable (address) disable (port) enable (address) disable (port) external bus width external bus width external bus width external bus width 8 bits 16 bits 8 bits 16 bits 8 bits 16 bits 8 bits 16 bits d07 to d00/ ad07 to ad00 d07 to d00 ad07 to ad00 p17 to p10/ d15 to d08/ ad15 to ad08 port d15 to d08 port d15 to d08 a15 to a08 ad15 to ad08 a15 to a08 ad15 to ad08 p27 to p20/ a07 to a00 a07 to a00 port p37 to p30/ a15 to a08 a15 to a08 p47 to p40/ a23 to a16 a23 to a16 port a23 to a16 port p57/ale ale ale rd rd rd p55/wrl wrl wrl p54/wrh port wrh port wrh port wrh port wrh p53/hrq hrq hrq p52/hak hak hak p51/rdy rdy rdy p50/clk clk clk
32 mb90640a series 2. uart0, 1 (sci) uart0, 1 are serial i/o ports that can be used for clk asynchronous (start-stop synchronization) or clk synchronous (i/o expansion serial) data transfer. the ports have the following features. ? full duplex, double buffered ? supports clk asynchronous (start-stop synchronization) and clk synchronous (i/o expansion serial) data transfer ? multi-processor mode support ? built-in dedicated baud rate generator clk asynchronous: 62500 bps/31250 bps/19230 bps/9615 bps/4808 bps/2404 bps/1202 bps clk synchronous: 2 mbps/1 mbps/500 kbps/250 kbps ? supports flexible baud rate setting using an external clock ? error detect function (parity, framing, and overrun) ? nrz type transmission signal ? intelligent i/o service support (1) register configuration address : md1 md0 cs2 cs1 cs0 scke soe bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w w w w r/w r/w initial value : 000020 h : 000024 h : 000021 h : 000025 h 00000-00 b address : pen p sbl cl a/d rec rxe txe bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000100 b address : d7 d6 d5 d4 d3 d2 d1 d0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : 000022 h : 000026 h : 000023 h : 000027 h xxxxxxxx b address : pe ore fre rdrf tdre rie tie bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r r r r r r/w r/w initial value 00001- 00 b : 000051 h : 000053 h address : div3 div2 div1 div0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 wwww initial value ---- 1111 b r/w r w x : readable and writable : read only : write only : unused : indeterminate smr0 smr1 scr0 scr1 sidr0 (read) / sodr0 (write) sidr1 (read) / sodr1 (write) cdcr0 cdcr1 ssr0 ssr1 ? serial mode register 0, 1 ? serial control register 0, 1 ? input data register 0, 1/output data register 0, 1 ? serial status register 0, 1 ? machine clock division control register for uart0, 1 (sci)
33 mb90640a series (2) block diagram control signals dedicated baud rate generator 16-bit timer 0 (internal connection) external clock sin clock select circuit receive interrupt (to cpu) transmit interrupt (to cpu) receive control circuit start bit detect circuit receive bit counter receive parity counter transmit control circuit transmit start circuit transmit bit counter transmit parity counter receive status evaluation circuit receive shifter receive complete transmit shifter transmit start receive error indication signal for ei 2 os (to cpu) sidr sodr internal data bus smr register md1 md0 cs2 cs1 cs0 scke soe scr register ssr register control signals transmit clock receive clock sot pen p sbl cl a/d rec rxe txe pe ore fre rdrf tdre rie tie sck
34 mb90640a series 3. 8/16-bit ppg 8/16-bit ppg contains the 8-bit reload timer module. the block performs ppg output in which the pulse output is controlled by the operation of the timer. the hardware consists of two 8-bit down-counters, four 8-bit reload registers, one 16-bit control register, two external pulse output pins, and two interrupt outputs. the ppg has the following functions. ? 8-bit ppg output in 2-channel independent operation mode: two independent ppg output channels are available. ? 16-bit ppg output operation mode: one 16-bit ppg output channel is available. ? 8+8-bit ppg output operation mode: variable-period 8-bit ppg output operation is available by using the output of channel 0 as the clock input to channel 1. ? ppg output operation: outputs pulse waveforms with variable period and duty ratio. can be used as a d/a converter in conjunction with an external circuit. (1) register configuration pen0 poe0 pie0 puf0 pcm1 pcm0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w initial value 0-000001 b 00000001 b xxxxxxxx b xxxxxxxx b address : pen1 pcs1 poe1 pie1 puf1 md1 md0 reserved bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w r/w r/w r/w r/w r/w r/w initial value : 000031 h : 000035 h : 000037 h address : bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w r/w r/w r/w r/w r/w r/w r/w initial value : 000034 h : 000036 h address : bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w initial value r/w x : readable and writable : unused : indeterminate : 000030 h address : ppgc0 ppgc1 prlh0 prlh1 prll0 prll1 reserved ? ppg0 operation mode control register ? ppg1 operation mode control register ? ppg0, ppg1 reload register h ? ppg0, ppg1 reload register l
35 mb90640a series (2) block diagram ppg0 output latch pcnt (down-counter) s r q output enable l/h selector prlbh0 ppgc0 peripheral clock divided by 16 peripheral clock divided by 4 peripheral clock prll0 prlh0 l-side data bus h-side data bus ppg0 clear invert pen0 reload ch.1 borrow irq count clock selection timebase counter output main clock divided by 512 l/h select pie 0 puf0 (operation mode control) ? 8/16-bit ppg (channel 0)
36 mb90640a series ppg1 output latch pcnt (down-counter) s r q output enable l/h selector prlbh1 ppgc1 peripheral clock prll1 prlh1 l-side data bus h-side data bus ppg1 clear invert pen1 reload channel 0 borrow irq timebase counter output main clock divided by 512 l/h select pie1 puf1 (operation mode control) count clock selection ? 8/16-bit ppg (channel 1)
37 mb90640a series 4. 16-bit reload timer (with event count function) the 16-bit reload timers consists of a 16-bit down-counter, a 16-bit reload register, input pin (tin), output pin (tot), and a control register. the input clock can be selected from one external clock and three types of internal clock. the output (tot) outputs a toggle waveform in reload mode and a rectangular waveform during counting in one-shot mode. the input (tin) functions as the event input in event count mode and as the trigger input or gate input in internal clock mode. input and output of timer pin tim0 to tim4 are set by way of the timer pin control register. this product has five internal 16-bit reload timer channels. (1) register configuration : 000039 h : 00003d h : 000059 h : 00005d h : 000061 h address : : 000038 h : 00003c h : 000058 h : 00005c h : 000060 h address : : 00003b h : 00003f h : 00005b h : 00005f h : 000063 h address : : 00003a h : 00003e h : 00005a h : 00005e h : 000062 h address : csl1 csl0 mod2 mod1 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w r/w r/w r/w initial value ---- 0000 b mod0 oute outl reld inte uf cnte trg bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000 b bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w initial value xxxxxxxx b bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 initial value xxxxxxxx b r/w x : readable and writable : unused : indeterminate tmr0/tmrlr0 tmr1/tmrlr1 tmr2/tmrlr2 tmr3/tmrlr3 tmr4/tmrlr4 tmr0/tmrlr0 tmr1/tmrlr1 tmr2/tmrlr2 tmr3/tmrlr3 tmr4/tmrlr4 tmcsr0 tmcsr1 tmcsr2 tmcsr3 tmcsr4 tmcsr0 tmcsr1 tmcsr2 tmcsr3 tmcsr4 ? timer control status register upper ? timer control status register lower ? 16-bit timer register upper/16-bit reload register upper ? 16-bit timer register lower/16-bit reload register lower
38 mb90640a series : 000066 h address : : 000065 h address : : 000064 h address : ote4 csc4 csb4 csa4 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value ---- 0100 b ote1 csc1 csb1 csa1 ote0 csc0 csb0 csa0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w initial value 00010000 b ote3 csc3 csb3 csa3 ote2 csc2 csb2 csa2 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 initial value 00110010 b r/w x : readable and writable : unused : indeterminate tpcr tpcr tpcr ? timer pin control register upper ? timer pin control register middle ? timer pin control register lower
39 mb90640a series (2) block diagram 16-bit reload register 16-bit down-counter uf clock selector reload out ctl csl1 csl0 mod2 mod1 mod0 16 8 16 2 3 2 in ctl f 2 3 f 2 1 f 2 5 3 peripheral clock prescaler clear exck gate re-trigger irq tot0 to tot4 tin0 to tin4 output enable serial baud rate a/d converter reld oute outl inte uf cnte trg clear i 2 osclr internal data bus 16-bit reload timer 0 tin0 tot0 16-bit reload timer 1 tin1 tot1 16-bit reload timer 2 tin2 tot2 16-bit reload timer 3 tin3 tot3 tim0 tim1 tim2 tim3 16-bit reload timer 4 tin4 tot4 tim4 note: timer channel and direction (i/o) can be selected for each pin. selector
40 mb90640a series 5. chip select function this module generates chip select signals to simplify connection of memory or i/o devices. the module has 8 chip select output pins. the hardware outputs the chip select signals from the pins when it detects access of an address in the areas specified in the pin registers. (1) register configuration (2) block diagram : 000049 h : 00004b h : 00004d h : 00004f h address : : 000048 h : 00004a h : 00004c h : 00004e h address : r/w r/w r/w r/w r/w r/w r/w r/w actl opel csa1 csa0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w initial value ---- 0000 b actl opel csa1 csa0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 initial value ---- 0000 b r/w : readable and writable : unused cscr1 cscr3 cscr5 cscr7 cscr0 cscr2 cscr4 cscr6 ? chip select control register 1, 3, 5, 7 ? chip select control register 0, 2, 4, 6 selector selector chip select control register 0 chip select control register 1 cs0 (for the program rom area) cs1 cs6 address (from cpu) address decoder address decoder a23 a16 a15 a08 a07 a00 decode signal program area decode selection setting selection setting selector selector chip select control register 6 chip select control register 7 cs7 selection setting selection setting
41 mb90640a series 6. dtp/external interrupts the dtp (data transfer peripheral) is a peripheral block that interfaces external peripherals to the f 2 mc-16l cpu. the dtp receives dma and interrupt processing requests from external peripherals and passes the requests to the f 2 mc-16l cpu to activate the extended intelligent i/o service or interrupt processing. two request levels (h and l) are provided for extended intelligent i/o service. for external interrupt requests, generation of interrupts on a rising or falling edge as well as on h, l levels can be selected, giving a total of four types. (1) register configuration (2) block diagram address : en7 en6 en5 en4 en3 en2 en1 en0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w initial value : 000028 h : 000029 h 00000000 b address : er7 er6 er5 er4 er3 er2 er1 er0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w r/w r/w r/w r/w r/w r/w r/w initial value xxxxxxxx b : 00002b h address : lb7 la7 lb6 la6 lb5 la5 lb4 la4 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000 b : 00002a h address : lb3 la3 lb2 la2 lb1 la1 lb0 la0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000 b r/w x : indeterminate : readable and writable elvr elvr eirr enir ? interrupt/dtp enable register ? interrupt/dtp source register ? request level setting register upper ? request level setting register lower 8 8 8 8 8 interrupt/dtp enable register interrupt/dtp register request level setting register gate request f/f edge detect circuit request input interrupt input internal data bus
42 mb90640a series 7. delayed interrupt generation module the delayed interrupt generation module is used to generate the task switching interrupt. interrupt requests to the f 2 mc-16l cpu can be generated and cleared by software using this module. (1) register configuration (2) block diagram : 00009f h address : r0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w initial value -------0 b r/w : readable and writable : unused dirr ? delayed interrupt generation/release register delayed interrupt generation/release register interrupt latch internal data bus
43 mb90640a series 8. rom mirror functional selection module rom mirror function selecting module can be refered to the upper 48 kbytes of ff bank which is wired rom at 00 bank by selecting the resister setting. (1) register configuration notes: ? the initial value of mb90v640a is 0 and that of mb90p641a, MB90641A is 1. ? not to access to this register while address 04000 h to 00ffff h are in operation. (2) block diagram : 00006f h address : mi bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w initial value -------* b w * : write only : unused : ??or ??(determined owing to the md0 to md2 pin level) romm ? rom mirror functional selection module rom mirror functional selection module ff bank rom 00 bank internal data bus address area address data
44 mb90640a series 9. watchdog timer and timebase timer the watchdog timer consists of a 2-bit watchdog counter, a control register, and a watchdog reset controller. the watchdog counter uses the carry-up signal from the 18-bit timebase timer as its clock source. in addition to the 18-bit timer, the timebase timer contains an interval interrupt control circuit. the timebase timer uses the main clock, regardless of the value of the mcs bit in the ckscr register. (1) register configuration (2) block diagram : 0000a8 h address : ponr stbr wrst erst srst wte wt1 wt0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rr rrr www initial value xxxxx111 b : 0000a9 h address : reserved tbie tbof tbr tbc1 tbc0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r/w r/w w r/w r/w initial value 1- - 00100 b r/w r w x : readable and writable : read only : write only : unused : indeterminate tbtc wdtc ? watchdog timer control register ? timebase timer control register tbtc tbc1 tbc0 tbr tbie tbof ponr stbr wrst erst srst selector and q selector 2-bit counter clr clr watchdog reset activation circuit wt1 wdtc wt0 wte 2 12 2 12 timebase interrupt s r 2 14 2 16 2 19 tbtres timebase timer clock input 2 14 2 16 2 19 of main clock (osc oscillator) wdgrst to internal reset activation circuit from power-on detection from hardware standby control circuit rst pin from the rst bit of the stbyc register internal data bus
45 mb90640a series 10. low-power control circuits (cpu intermittent operation function, oscillation stabilization delay time, and clock multiplier function) the following operation modes are available: pll clock mode, pll sleep mode, timer mode, main clock mode, main sleep mode, stop mode, and hardware standby mode. operation modes other than pll clock mode are classified as low-power consumption modes. in main clock mode and main sleep mode, the device operates on the main clock only (osc oscillator clock). the pll clock (vco oscillator clock) is stopped in these modes and the main clock divided by 2 is used as the operating clock. in pll sleep mode and main sleep mode, the cpus operating clock only is stopped and other elements continue to operate. in timer mode, only the timebase timer operates. stop mode and hardware standby mode stop the oscillator. these modes maintain existing data with minimum power consumption. the cpu intermittent operation function provides an intermittent clock to the cpu when register, internal memory, internal resource, or external bus access is performed. this function reduces power consumption by lowering the cpu execution speed while still providing a high-speed clock to internal resources. the pll clock multiplier ratio can be set to 1, 2, 3, 4 by the cs1, cs0 bits. the ws1, ws0 bits set the delay time to wait for the main clock oscillation to stabilize when recovering from stop mode or hardware standby mode. (1) register configuration : 0000a0 h address : stp slp spl rst cg1 cg0 reserved reserved bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 w w r/w w r/w r/w initial value 00011000 b : 0000a1 h address : mcm ws1 ws0 reserved reserved mcs cs1 cs0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 r r/w r/w r/w r/w r/w initial value 11111100 b r/w r w : readable and writable : read only : write only ckscr lpmcr ? low-power consumption mode control register ? clock select register
46 mb90640a series (2) block diagram main clock (osc oscillator) mcm mcs cs1 cs0 cg1 cg0 slp stp pll multiplier circuit 1234 1/2 cpu clock selector cycle selection circuit for the cpu intermittent operation function standby control circuit rst release hst activate ws1 ws0 oscillation stabilization delay time selector spl internal reset generation circuit rst pin high impedance control circuit cpu clock generator peripheral clock generator timebase timer 2 4 2 13 2 15 2 18 clock input 2 19 2 16 2 14 2 12 lpmcr lpmcr ckscr ckscr ckscr lpmcr lpmcr 0/9/17/33 intermittent cycle selection cpu clock peripheral clock hst pin interrupt request or rst timebase clock pin hi-z rst pin internal rst to watchdog timer wdgrst internal data bus
47 mb90640a series main mcs = 1 mcm = 1 cs1/0 = xx main ? pllx mcs = 0 mcm = 1 cs1/0 = xx pll1 ? main mcs = 1 mcm = 0 cs1/0 = 00 pll2 ? main mcs = 1 mcm = 0 cs1/0 = 01 pll3 ? main mcs = 1 mcm = 0 cs1/0 = 10 pll4 ? main mcs = 1 mcm = 0 cs1/0 = 11 pll multiplier = 1 mcs = 0 mcm = 0 cs1/0 = 00 pll multiplier = 2 mcs = 0 mcm = 0 cs1/0 = 01 pll multiplier = 3 mcs = 0 mcm = 0 cs1/0 = 10 pll multiplier = 4 mcs = 0 mcm = 0 cs1/0 = 11 (1) (6) (7) (7) (7) (7) (2) (3) (4) (6) (6) (5) (6) (6) power-on (1) (2) (3) (4) (5) (6) (7) mcs bit cleared pll clock oscillation stabilization delay complete and cs1/0 = 00 pll clock oscillation stabilization delay complete and cs1/0 = 01 pll clock oscillation stabilization delay complete and cs1/0 = 10 pll clock oscillation stabilization delay complete and cs1/0 = 11 mcs bit set (including a hardware standby or watchdog reset) pll clock and main clock synchronized timing ? state transition diagram for clock selection
48 mb90640a series 11. interrupt controller the interrupt control registers are located in the interrupt controller. an interrupt control register is provided for each i/o with an interrupt function. the registers have the following three functions. ? set the interrupt level of the corresponding peripheral. ? select whether to treat interrupts from the corresponding peripheral as standard interrupts or activate the extended intelligent i/o service. ? select the extended intelligent i/o service channel. (1) register configuration note: do not access these registers using read-modify-write instructions as this can cause misoperation. : icr01 icr03 icr05 icr07 icr09 icr11 icr13 icr15 address ics3 ics2 ics1 or s1 ics0 or s0 ise il2 il1 il0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 w w r/w r/w r/w r/w r/w r/w initial value : 0000b1 h : 0000b3 h : 0000b5 h : 0000b7 h : 0000b9 h : 0000bb h : 0000bd h : 0000bf h ics3 ics2 ics1 or s1 ics0 or s0 ise il2 il1 il0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 00000111 b : icr00 icr02 icr04 icr06 icr08 icr14 address w w r/w r/w r/w r/w r/w r/w initial value : 0000b0 h : 0000b2 h : 0000b4 h : 0000b6 h : 0000b8 h : 0000be h 00000111 b r/w w : readable and writable : write only ? interrupt control register 01, 03, 05, 07, 09, 11, 13, 15 ? interrupt control register 00, 02, 04, 06, 08, 10, 12, 14
49 mb90640a series (2) block diagram 4 4 4 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ise il2 il1 il0 determine priority of interrupt or i 2 os interrupt /i 2 os request (peripheral resource) 32 s1 s0 detect i 2 os completion condition i 2 os completion condition 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 ics3 ics2 ics1 ics0 i 2 os vector selection i 2 os vector (cpu) (cpu) interrupt level 4 i 2 os selection internal data bus
50 mb90640a series 12. external bus terminal control circuit this circuit controls the external bus terminals intended to extend outwardly the cpus address/data bus. (1) register configuration (2) block diagram : 0000a5 h address : ior1 ior0 hmr1 hmr0 lmr1 lmr0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ww ww w w initial value 0011- - 00 b : 0000a6 h address : e23 e22 e21 e20 e19 e18 e17 e16 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wwwwwwww initial value 00000000 b : 0000a7 h address : lmbs wre hmbs iobs hde rye cke bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 wwwwwww initial value -00*0000 b w x * : write only : unused : indeterminate : ??or ??(determined owing to the md0 to md2 pin level) ecsr hacr arsr ? register for selection of auto ready function ? register for control of external address output ? register for selection of bus control signal access control data control port 0 data register port 0 direction register access control access control rb port 0 pin port 1 pin port 2 pin port 3 pin port 4 pin port 5 pin port 0 port 1 port 2 port 3 port 4 port 5
51 mb90640a series n electrical characteristics 1. absolute maximum rating (v ss = av ss = 0.0 v) *1: v i and v o must not exceed v cc + 0.3 v. *2: the maximum output current must not be exceeded at any individual pin. *3: the average output current is the operating current running through an appropriate pin the operating rate. *4: the average total output current is the operating current running through all the appropriate pins the operating rate. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol value unit remarks min. max. power supply voltage v cc v ss C 0.3 v ss + 6.0 v input voltage* 1 v i v ss C 0.3 v cc + 0.3 v output voltage* 1 v o v ss C 0.3 v cc + 0.3 v l level maximum output current* 2 i ol 15ma l level average output current* 3 i olav 4ma l level total maximum output current s i ol 100 ma l level total average output current* 4 s i olav 50ma h level maximum output current* 2 i oh C15 ma h level average output current* 3 i ohav C4ma h level total maximum output current s i oh C100 ma h level total average output current* 4 s i ohav C50 ma power consumption p d +150 mw MB90641A +400 mw mb90p641a operating temperature t a C40 +85 c storage temperature tstg C55 +150 c
52 mb90640a series 2. recommended operating conditions (v ss = av ss = 0.0 v) * : target pins are p60 to p67, p71 to p76, p80 to p86, p90 to p95, hst , and rst . (when used as general purpose pins) warning: recommended operating conditions are normal operating ranges for the semiconductor device. all the devices electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representative beforehand. parameter symbol value unit remarks min. max. power supply voltage v cc 4.5 5.5 v for normal operation v cc 3.5 5.5 v to maintain statuses in stop mode h level input voltage v ih 2.2 v cc + 0.3 v ttl level input pins v ihc 0.7 v cc v cc + 0.3 v cmos level input pins v ihs 0.8 v cc v cc + 0.3 v hysteresis input pins* v ihm v cc C 0.3 v cc + 0.3 v md input pin l level input voltage v il v ss C 0.3 0.8 v ttl level input pins v ilc v ss C 0.3 0.3 v cc v cmos level input pins v ils v ss C 0.3 0.2 v cc v hysteresis input pins* v ilm v ss C 0.3 v ss + 0.3 v md input pin smoothing capacitor c s 0.1 1.0 m f use the ceramic capacitor or the capacitor which has the similar frequency characteristic as ceramic capacitor. when attach the smoothing capacitor to v cc , use the capacitor whose capacitance is larger than c s . operating temperature t a C40 +85 c
53 mb90640a series 3. dc characteristics (v cc = 4.5 v to 5.5 v, v ss = 0.0 v, t a = C40c to +85c) * : because the current values are tentative values, they are subject to change without notice due to our efforts to improve the characteristics of these devices. parameter symbol pin name condition value unit remarks min. typ. max. h level output voltage v oh other than p60 to p67 v cc = 4.5 v, i oh = C4.0 ma v cc C 0.5 v l level output voltage v ol all output pins v cc = 4.5 v, i ol = 4.0 ma 0.4v input leakage current i il other than p60 to p67 v cc = 5.5 v, v ss < v i < v cc C5 5 m a open-drain output leakage current i leak p60 to p67 0.1 5 m a pull-up resistance r up 15 50 100 k w pull-down resistance r down 15 50 200 k w power supply current* i cc v cc = 5.0 v internal 16 mhz operation normal operation 5070ma mb90v640a/ p641a 1520ma MB90641A i ccs internal 16 mhz operation sleep mode 2530ma mb90v640a/ p641a 510ma MB90641A i cch t a = +25 c stop mode 0.110 m a mb90v640a/ p641a 520 m a MB90641A input capacitance c in other than v cc , v ss , c 10pf
54 mb90640a series 4. ac characteristics (1) clock timing (v cc = 4.5 v to 5.5 v, v ss = 0.0 v, t a = C40c to +85c) * : the frequency variation ratio is the maximum variation from the specified central frequency when the multiplier pll is locked. the value is expressed as a proportion. parameter symbol pin name conditions value unit remarks min. max. source oscillation frequency f c x0, x1 317mhz source oscillation cycle time t c x0, x1 58.8 333 ns frequency variation ratio* (when locked) d f 5% input clock pulse width p wh p wl x0 10 ns the duty ratio should be in the range 30 to 70% input clock rise time and fall time t cr t cf x0 5ns internal operating clock frequency f cp 1.5 17 mhz internal operating clock cycle time t cp 58.8 666 ns d f = 100 (%) f 0 central frequency f 0 + a a ? a 0.8 v cc 0.2 v cc t c t cf t cr p wh p wl ? clock timing
55 mb90640a series 34 8 1617 16 17 12 9 8 4 multiply multiply by 4 by 3 no multiplier oscillation clock f c (mhz) relationship between the oscillation frequency and internal operating clock frequency multiply by 1 multiply by 2 : normal operation assurance range : pll operation assurance range internal clock f cp (mhz) 5.5 4.5 817 4 1.5 internal clock f cp (mhz) relationship between the internal operating clock frequency and supply voltage power supply v cc (v) ? pll operation assurance range
56 mb90640a series the ac characteristics are for the following measurement reference voltages. (2) clock output timing (v cc = 4.5 v to 5.5 v, v ss = 0.0 v, t a = C40c to +85c) t cp : see (1) clock timing. parameter symbol pin name conditions value unit remarks min. max. cycle time t cyc clk t cp ns clk - ? clk t chcl t cp /2 C 20 t cp /2 + 20 ns hysteresis input pins 0.8 v cc 0.2 v cc other than hysteresis/md input pins 0.7 v cc 0.3 v cc output pins 2.4 v 0.8 v ? input signal waveform ? output signal waveform t cyc t chcl clk 0.8 v 2.4 v 2.4 v
57 mb90640a series (3) recommended resonator manufacturers x0 x1 c 1 c 2 *2 *2 far *1: fujitsu acoustic resonator *1 r inquiry: fujitsu limited far part number (built-in capacitor type) frequency (mhz) dumping resistor initial deviation of far frequency (t a = +25 c) temperature characteristics of far frequency (t a = C20 c to +60 c) loading capacitors* 2 far-c4cc-02000-l20 2.00 1 k w 0.5% 0.5% built-in far-c4ca-04000-m01 4.00 0.5% 0.5% far-c4cb-08000-m02 8.00 0.5% 0.5% far-c4cb-10000-m02 10.00 0.5% 0.5% far-c4cb-16000-m02 16.00 0.5% 0.5% ? sample application of piezoelectric resonator (far family)
58 mb90640a series (continued) x0 x1 c 1 c 2 r * ? sample application of ceramic resonator resonator manufacturer* resonator frequency (mhz) c 1 (pf) c 2 (pf) r kyocera corporation kbr-2.0ms 2.00 150 150 not required pbrc2.00a 150 150 not required kbr-4.0msa 4.00 33 33 680 w kbr-4.0mks built-in built-in 680 w pbrc4.00a 33 33 680 w pbrc4.00b built-in built-in 680 w kbr-6.0msa 6.00 33 33 not required kbr-6.0mks built-in built-in not required pbrc6.00a 33 33 not required pbrc6.00b built-in built-in not required kbr-8.0m 8.00 33 33 560 w pbrc8.00a 33 33 not required pbrc8.00b built-in built-in not required kbr-10.0m 10.00 33 33 330 w pbrc10.00b built-in built-in 680 w kbr-12.0m 12.00 33 33 330 w pbrc12.00b built-in built-in 680 w
59 mb90640a series (continued) inquiry: kyocera corporation avx corporation north american sales headquarters: tel 1-803-448-9411 avx limited european sales headquarters: tel 44-1252-770000 avx/kyocera h.k. ltd. asian sales headquarters: tel 852-363-3303 murata mfg. co., ltd. murata electronics north america, inc.: tel 1-404-436-1300 murata europe management gmbh: tel 49-911-66870 murata electronics singapore (pte.) ltd.: tel 65-758-4233 resonator manufacturer resonator frequency (mhz) c 1 (pf) c 2 (pf) r murata mfg. co., ltd. csa2.00mg040 2.00 100 100 not required cst2.00mg040 built-in built-in not required csa4.00mg040 4.00 100 100 not required cst4.00mgw040 built-in built-in not required csa6.00mg 6.00 30 30 not required cst6.00mgw built-in built-in not required csa8.00mtz 8.00 30 30 not required cst8.00mtw built-in built-in not required csa10.00mtz 10.00 30 30 not required cst10.00mtw built-in built-in not required csa12.00mtz 12.00 30 30 not required cst12.00mtw built-in built-in not required csa16.00mxz040 16.00 15 15 not required cst16.00mxw0c3 built-in built-in not required csa20.00mxz040 20.00 10 10 not required csa24.00mxz040 24.00 5 5 not required csa32.00mxz040 32.00 5 5 not required
60 mb90640a series (4) reset and hardware standby inputs (v cc = 4.5 v to 5.5 v, v ss = 0.0 v, t a = C40c to +85c) t cp : see (1) clock timing. parameter symbol pin name conditions value unit remarks min. max. reset input time t rstl rst 16 t cp ns hardware standby input time t hstl hst 16 t cp ns rst hst 0.2 v cc 0.2 v cc t rstl , t hstl c l pin c l : load capacity during testing for clk and ale, c l = 30 pf for address and data buses (ad15 to ad00), rd and wr, c l = 80 pf ? conditions for measurement of ac reference
61 mb90640a series (5) power on supply specifications (power-on reset) (v cc = 4.5 v to 5.5 v, v ss = 0.0 v, t a = C40c to +85c) * : v cc should be lower than 0.2 v before power supply rise. notes: ? the above values are the values required for a power-on reset. ? when hst = l, this standard must be followed to turn on power supply for power-on reset whether or not necessary. ? the device has built-in registers which are initialized only by power-on reset. for possible initialization of these registers, turn on power supply according to this standard. parameter symbol pin name conditions value unit remarks min. max. power supply rise time t r v cc 0.05 30 ms power supply cut-off time t off v cc 50 ms for repetition of the operation 2.7 v t r 0.2 v 0.2 v 0.2 v v cc t off 5.0 v 3.5 v v ss v cc the gradient should be no more than 50 mv/ms. holding ram data abrupt changes in the power supply voltage may cause a power-on reset. when changing the power supply voltage during operation, the change should be as smooth as possible, as shown in the following figure.
62 mb90640a series (6) bus timing (read) (v cc = 4.5 v to 5.5 v, v ss = 0.0 v, t a = C40c to +85c) t cp : see (1) clock timing. parameter symbol pin name conditions value unit remarks min. max. ale pulse width t lhll ale t cp /2 C 20 ns valid address ? ale time t av ll address t cp /2 C 20 ns ale ? address valid time t llax address t cp /2 C 15 ns valid address ? rd time t av rl address t cp C 15 ns valid address ? valid data input t avdv address/ data 5 t cp /2 C 60 ns rd pulse width t rlrh rd 3 t cp /2 C 20 ns rd ? valid data input t rldv data 3 t cp /2 C 60 ns rd - ? data hold time t rhdx data 0 ns rd - ? ale - time t rhlh rd , ale t cp /2 C 15 ns rd - ? address valid time t rhax address, rd t cp /2 C 10 ns valid address ? clk - time t av ch address, clk t cp /2 C 20 ns rd ? clk - time t rlch rd , clk t cp /2 C 20 ns ale ? rd time t llrl ale, rd t cp /2 C 15 ns
63 mb90640a series clk ale rd address read data t lhll t avrl t llrl t rlrh t rhax t rhdx 2.4 v 2.4 v 2.4 v 0.8 v 2.4 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 2.2 v 2.2 v 0.8 v a23 to a16 d15 to d00 multiplex mode 0.8 v read data t rhax t rhdx t avdv t rldv 0.8 v 2.4 v 0.8 v 2.4 v 2.2 v 2.2 v 0.8 v a23 to a00 non-multiplex mode 0.8 v 0.8 v 2.4 v t avch t rlch t avll t llax t rhlh t avdv t rldv t avdv
64 mb90640a series (7) bus timing (write) (v cc = 4.5 v to 5.5 v, v ss = 0.0 v, t a = C40c to +85c) t cp : see (1) clock timing. parameter symbol pin name conditions value unit remarks min. max. valid address ? wr time t avw l address t cp C 15 ns wr pulse width t wlwh wrl , wrh 3 t cp /2 C 20 ns valid data output ? wr - time t dvwh data 3 t cp /2 C 20 ns wr - ? data hold time t whdx data 20 ns multiplex mode 30 ns non-multiplex mode wr - ? address valid time t whax address t cp /2 C 10 ns wr - ? ale - time t whlh wrl , wrh , ale t cp /2 C 15 ns wr ? clk - time t wlch wrl , wrh , clk t cp /2 C 20 ns clk ale wr (wrl, wrh) address write data t whdx t whax t wlwh t avwl 0.8 v 2.4 v a23 to a16 ad15 to ad00 2.4 v 2.4 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v multiplex mode write data t whdx a23 to a00 d15 to d00 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v non-multiplex mode t wlch t whlh t whdx t whax t dvwh t dvwh
65 mb90640a series (8) ready input timing (v cc = 4.5 v to 5.5 v, v ss = 0.0 v, t a = C40c to +85c) note: use the auto-ready function if the setup time at fall of the rdy is too short. parameter symbol pin name conditions value unit remarks min. max. rdy setup time t ryhs rdy v cc = 5.0 v 10% 45 ns rdy hold time t ryhh 0ns clk ale rdy (wait cycle) rdy (no wait cycle) rd/wr 2.4 v 2.4 v t ryhs t ryhs t ryhs t ryhh 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc
66 mb90640a series (9) hold timing (v cc = 4.5 v to 5.5 v, v ss = 0.0 v, t a = C40c to +85c) t cp : see (1) clock timing. note: after reading hrq, more than one cycle is required before changing hak . parameter symbol pin name conditions value unit remarks min. max. pin floating ? hak time t xhal hak 30t cp ns hak - ? pin valid time t hahv hak t cp 2 t cp ns high impedance hak pin 0.8 v 2.4 v t xhal t hahv
67 mb90640a series (10) i/o extended serial timing (v cc = 4.5 v to 5.5 v, v ss = 0.0 v, t a = C40c to +85c) notes: ? these are the ac characteristics for clk synchronous mode. ?c l is the load capacitance connected to the pin at testing. ?t cp is the machine cycle period (unit: ns). ? the values in the upper table are targets. parameter symbol pin name conditions value unit remarks min. max. serial clock cycle time t scyc sck0, sck1 c l = 80 pf + 1 ttl for the internal shift clock mode output pin. 8 t cp ns sck ? sot delay time t slov sck0, sck1 sot0, sot1 C80 80 ns valid sin ? sck - t ivsh sck0, sck1 sin0, sin1 100 ns sck - ? valid sin hold time t shix sck0, sck1 sin0, sin1 60 ns serial clock h pulse width t shsl sck0, sck1 c l = 80 pf + 1 ttl for the external shift clock mode output pin. 4 t cp ns serial clock l pulse width t slsh sck0, sck1 4 t cp ns sck ? sot delay time t slov sck0, sck1 sot0, sot1 150ns valid sin ? sck - t ivsh sck0, sck1 sin0, sin1 60 ns sck - ? valid sin hold time t shix sck0, sck1 sin0, sin1 60 ns
68 mb90640a series sck sot sin t scyc t slov t ivsh t shix 2.4 v 0.8 v cc 0.8 v 0.8 v 2.4 v 0.8 v 0.2 v cc 0.8 v cc 0.2 v cc sck sot sin t slsh t slov t ivsh t shix t shsl 0.8 v cc 2.4 v 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc ? internal shift clock mode ? external shift clock mode
69 mb90640a series (11) timer input timing (v cc = 4.5 v to 5.5 v, v ss = 0.0 v, t a = C40c to +85c) t cp : see (1) clock timing. (12) timer output timing (v cc = 4.5 v to 5.5 v, v ss = 0.0 v, t a = C40c to +85c) parameter symbol pin name conditions value unit remarks min. max. input pulse width t tiwh t tiwl tim0 to tim4 4 t cp ns parameter symbol pin name conditions value unit remarks min. max. clk - ? t out change timing t to tim0 to tim4 30 ns 0.8 v cc 0.2 v cc t tiwh 0.2 v cc 0.8 v cc t tiwl clk t out t to 2.4 v 2.4 v 0.8 v
70 mb90640a series (13) trigger input timing (v cc = 4.5 v to 5.5 v, v ss = 0.0 v, t a = C40c to +85c) t cp : see (1) clock timing. (14) chip select output timing (v cc = 4.5 v to 5.5 v, v ss = 0.0 v, t a = C40c to +85c) t cp : see (1) clock timing. parameter symbol pin name conditions value unit remarks min. max. input pulse width t trgl int0 to int7 5 t cp ns parameter symbol pin name conditions value unit remarks min. max. chip select enabled ? valid data input time t svdv cs0 to cs7 d15 to d00 5 t cp /2 C 60 ns rd - ? chip select enabled time t rhsv cs0 to cs7 rd t cp /2 C 10 ns wr - ? chip select enabled time t whsv cs0 to cs7 wr t cp /2 C 10 ns enabled chip select ? clk - time t svch cs0 to cs7 clk t cp /2 C 20 ns 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t trgh t trgl
71 mb90640a series clk rd read data t svch 2.4 v a23 to a00 cs0 to cs7 d15 to d00 2.4 v 2.4 v 2.4 v 0.8 v 2.4 v 0.8 v write data wr (wrl, wrh) d15 to d00 t rhsv t whsv t svdv
72 mb90640a series n examples characteristics 1. MB90641A 0.45 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0.0 v cc - v oh (v) i oh (ma) ? ? ? ? ? v cc - v oh vs. i oh v cc = 3.0 v t a = +25 c v cc = 3.5 v v cc = 4.0 v v cc = 4.5 v v cc = 5.0 v v cc = 5.5 v 0.45 0.4 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0.0 v ol (v) i ol (ma) 23 456 v ol vs. i ol t a = +25 c v cc = 3.0 v v cc = 3.5 v v cc = 4.0 v v cc = 4.5 v v cc = 5.0 v v cc = 5.5 v 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 v in (v) v cc (v) 3 3.5 4 4.5 5 5.5 t a = +25 c v in vs. v cc 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 v in (v) v cc (v) 3 3.5 4 4.5 5 5.5 v in vs. v cc t a = +25 c v ihs v ils v ihs : v ils : thershold when input voltage in hysteresis characteristics is set to ??level thershold when input voltage in hysteresis characteristics is set to ??level i cc (ma) i cc vs. v cc 24 22 20 18 16 14 12 10 8 6 4 2 0 3.0 4.0 5.0 6.0 v cc (v) f cp = 16 mhz f cp = 8 mhz f cp = 4 mhz f cp = 2 mhz t a = +25 c i ccs ( ma) i ccs vs. v cc 6 5 4 3 2 1 0 3.0 4.0 5.0 6.0 v cc (v) f cp = 16 mhz f cp = 8 mhz f cp = 4 mhz f cp = 2 mhz t a = +25 c (3) h level input voltage/l level input voltage (cmos input) (4) h level input voltage/l level input voltage (hysteresis input) (1) h level output voltage (2) l level output voltage (5) power supply current (f cp = internal frequency)
73 mb90640a series 2. mb90p641a v oh (v) v cc = 4.5 v v cc = 5.0 v i oh ( ma ) 8 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 v oh vs. i oh 4 6 2 v cc = 4.0 v v cc = 3.0 v v cc = 2.7 v v cc = 3.5 v t a = +25 c v ol (v) v cc = 4.5 v v cc = 5.0 v i ol (ma) 8 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 v ol vs. i ol 46 2 v cc = 4.0 v v cc = 3.0 v v cc = 2.7 v v cc = 3.5 v t a = +25 c 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 v in (v) v cc (v) 23 456 v in vs. v cc t a = +25 c v ihs : v ils : thershold when input voltage in hysteresis characteristics is set to ??level thershold when input voltage in hysteresis characteristics is set to ??level 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 v in (v) v cc (v) 23 456 t a = +25 c v in vs. v cc v ihs v ils (3) h level input voltage/l level input voltage (cmos input) (4) h level input voltage/l level input voltage (hysteresis input) (1) h level output voltage (2) l level output voltage
74 mb90640a series (5) power supply current (f cp = internal frequency) (6) pull-up resistance i cc (ma) i cc vs. v cc 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 3.0 4.0 5.0 6.0 v cc (v) f cp = 16 mhz f cp = 12.5 mhz f cp = 8 mhz f cp = 4 mhz t a = +25 c i ccs (ma) i ccs vs. v cc 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3.0 4.0 5.0 6.0 v cc (v) f cp = 16 mhz f cp = 12.5 mhz f cp = 8 mhz f cp = 4 mhz t a = +25 c 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1000 r (k ) v cc (v) 100 10 2.5 t a = +25 c r vs. v cc
75 mb90640a series n instructions (340 instructions) table 1 explanation of items in tables of instructions item meaning mnemonic upper-case letters and symbols: represented as they appear in assembler. lower-case letters: replaced when described in assembler. numbers after lower-case letters: indicate the bit width within the instruction. # indicates the number of bytes. ~ indicates the number of cycles. m : when branching n : when not branching see table 4 for details about meanings of other letters in items. rg indicates the number of accesses to the register during execution of the instruction. it is used calculate a correction value for intermittent operation of cpu. b indicates the correction value for calculating the number of actual cycles during execution of the instruction. (table 5) the number of actual cycles during execution of the instruction is the correction value summed with the value in the ~ column. operation indicates the operation of instruction. lh indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator. z : transfers 0. x : extends with a sign before transferring. C : transfers nothing. ah indicates special operations involving the upper 16 bits in the accumulator. * : transfers from al to ah. C:no transfer. z : transfers 00 h to ah. x : transfers 00 h or ff h to ah by signing and extending al. i indicates the status of each of the following flags: i (interrupt enable), s (stack), t (sticky bit), n (negative), z (zero), v (overflow), and c (carry). * : changes due to execution of instruction. C : no change. s : set by execution of instruction. r : reset by execution of instruction. s t n z v c rmw indicates whether the instruction is a read-modify-write instruction. (a single instruction that reads data from memory, etc., processes the data, and then writes the result to memory.) * : instruction is a read-modify-write instruction. C : instruction is not a read-modify-write instruction. note: a read-modify-write instruction cannot be used on addresses that have different meanings depending on whether they are read or written.
76 mb90640a series table 2 explanation of symbols in tables of instructions (continued) symbol meaning a 32-bit accumulator the bit length varies according to the instruction. byte : lower 8 bits of al word : 16 bits of al long : 32 bits of al:ah ah al upper 16 bits of a lower 16 bits of a sp stack pointer (usp or ssp) pc program counter pcb program bank register dtb data bank register adb additional data bank register ssb system stack bank register usb user stack bank register spb current stack bank register (ssb or usb) dpr direct page register brg1 dtb, adb, ssb, usb, dpr, pcb, spb brg2 dtb, adb, ssb, usb, dpr, spb ri r0, r1, r2, r3, r4, r5, r6, r7 rwi rw0, rw1, rw2, rw3, rw4, rw5, rw6, rw7 rwj rw0, rw1, rw2, rw3 rli rl0, rl1, rl2, rl3 dir compact direct addressing addr16 addr24 ad24 0 to 15 ad24 16 to 23 direct addressing physical direct addressing bit 0 to bit 15 of addr24 bit 16 to bit 23 of addr24 io i/o area (000000 h to 0000ff h ) imm4 imm8 imm16 imm32 ext (imm8) 4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data signed and extended from 8-bit immediate data disp8 disp16 8-bit displacement 16-bit displacement bp bit offset vct4 vct8 vector number (0 to 15) vector number (0 to 255) ( )b bit address
77 mb90640a series (continued) table 3 effective address fields note: the number of bytes in the address extension is indicated by the + symbol in the # (number of bytes) column in the tables of instructions. symbol meaning rel branch specification relative to pc ear eam effective addressing (codes 00 to 07) effective addressing (codes 08 to 1f) rlst register list code notation address format number of bytes in address extension * 00 01 02 03 04 05 06 07 r0 r1 r2 r3 r4 r5 r6 r7 rw0 rw1 rw2 rw3 rw4 rw5 rw6 rw7 rl0 (rl0) rl1 (rl1) rl2 (rl2) rl3 (rl3) register direct ea corresponds to byte, word, and long-word types, starting from the left 08 09 0a 0b @rw0 @rw1 @rw2 @rw3 register indirect 0 0c 0d 0e 0f @rw0 + @rw1 + @rw2 + @rw3 + register indirect with post-increment 0 10 11 12 13 14 15 16 17 @rw0 + disp8 @rw1 + disp8 @rw2 + disp8 @rw3 + disp8 @rw4 + disp8 @rw5 + disp8 @rw6 + disp8 @rw7 + disp8 register indirect with 8-bit displacement 1 18 19 1a 1b @rw0 + disp16 @rw1 + disp16 @rw2 + disp16 @rw3 + disp16 register indirect with 16-bit displacement 2 1c 1d 1e 1f @rw0 + rw7 @rw1 + rw7 @pc + disp16 addr16 register indirect with index register indirect with index pc indirect with 16-bit displacement direct address 0 0 2 2
78 mb90640a series table 4 number of execution cycles for each type of addressing note: (a) is used in the ~ (number of states) column and column b (correction value) in the tables of instructions. table 5 correction values for number of cycles used to calculate number of actual cycles notes: ? (b), (c), and (d) are used in the ~ (number of states) column and column b (correction value) in the tables of instructions. ? when the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. table 6 correction values for number of cycles used to calculate number of program fetch cycles notes: ? when the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. ? because instruction execution is not slowed down by all program fetches in actuality, these correction values should be used for worst case calculations. code operand (a) number of register accesses for each type of addressing number of execution cycles for each type of addressing 00 to 07 ri rwi rli listed in tables of instructions listed in tables of instructions 08 to 0b @rwj 2 1 0c to 0f @rwj + 4 2 10 to 17 @rwi + disp8 2 1 18 to 1b @rwj + disp16 2 1 1c 1d 1e 1f @rw0 + rw7 @rw1 + rw7 @pc + disp16 addr16 4 4 2 1 2 2 0 0 operand (b) byte (c) word (d) long number of cycles number of access number of cycles number of access number of cycles number of access internal register +0 1 +0 1 +0 2 internal memory even address internal memory odd address +0 +0 1 1 +0 +2 1 2 +0 +4 2 4 even address on external data bus (16 bits) odd address on external data bus (16 bits) +1 +1 1 1 +1 +4 1 2 +2 +8 2 4 external data bus (8 bits) +1 1 +4 2 +8 4 instruction byte boundary word boundary internal memory +2 external data bus (16 bits) +3 external data bus (8 bits) +3
79 mb90640a series table 7 transfer instructions (byte) [41 instructions] note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah i s t n z v c rmw mov a, dir mov a, addr16 mov a, ri mov a, ear mov a, eam mov a, io mov a, #imm8 mov a, @a mov a, @rli+disp8 movn a, #imm4 movx a, dir movx a, addr16 movx a, ri movx a, ear movx a, eam movx a, io movx a, #imm8 movx a, @a movx a,@rwi+disp8 movx a, @rli+disp8 mov dir, a mov addr16, a mov ri, a mov ear, a mov eam, a mov io, a mov @rli+disp8, a mov ri, ear mov ri, eam mov ear, ri mov eam, ri mov ri, #imm8 mov io, #imm8 mov dir, #imm8 mov ear, #imm8 mov eam, #imm8 mov @al, ah /mov @a, t xch a, ear xch a, eam xch ri, ear xch ri, eam 2 3 1 2 2+ 2 2 2 3 1 2 3 2 2 2+ 2 2 2 2 3 2 3 1 2 2+ 2 3 2 2+ 2 2+ 2 3 3 3 3+ 2 2 2+ 2 2+ 3 4 2 2 3+ (a) 3 2 3 10 1 3 4 2 2 3+ (a) 3 2 3 5 10 3 4 2 2 3+ (a) 3 10 3 4+ (a) 4 5+ (a) 2 5 5 2 4+ (a) 3 4 5+ (a) 7 9+ (a) 0 0 1 1 0 0 0 0 2 0 0 0 1 1 0 0 0 0 1 2 0 0 1 1 0 0 2 2 1 2 1 1 0 0 1 0 0 2 0 4 2 (b) (b) 0 0 (b) (b) 0 (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 0 (b) (b) (b) 0 (b) 0 (b) 0 (b) (b) 0 (b) (b) 0 2 (b) 0 2 (b) byte (a) ? (dir) byte (a) ? (addr16) byte (a) ? (ri) byte (a) ? (ear) byte (a) ? (eam) byte (a) ? (io) byte (a) ? imm8 byte (a) ? ((a)) byte (a) ? ((rli)+disp8) byte (a) ? imm4 byte (a) ? (dir) byte (a) ? (addr16) byte (a) ? (ri) byte (a) ? (ear) byte (a) ? (eam) byte (a) ? (io) byte (a) ? imm8 byte (a) ? ((a)) byte (a) ? ((rwi)+disp8) byte (a) ? ((rli)+disp8) byte (dir) ? (a) byte (addr16) ? (a) byte (ri) ? (a) byte (ear) ? (a) byte (eam) ? (a) byte (io) ? (a) byte ((rli) +disp8) ? (a) byte (ri) ? (ear) byte (ri) ? (eam) byte (ear) ? (ri) byte (eam) ? (ri) byte (ri) ? imm8 byte (io) ? imm8 byte (dir) ? imm8 byte (ear) ? imm8 byte (eam) ? imm8 byte ((a)) ? (ah) byte (a) ? (ear) byte (a) ? (eam) byte (ri) ? (ear) byte (ri) ? (eam) z z z z z z z z z z x x x x x x x x x x C C C C C C C C C C C C C C C C C z z C C * * * * * * * C * * * * * * * * * C * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * r * * * * * * * * * * * * * * * * * * * * * * C C * C * C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C * C * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
80 mb90640a series table 8 transfer instructions (word/long word) [38 instructions] note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah i s t n z v c rmw movw a, dir movw a, addr16 movw a, sp movw a, rwi movw a, ear movw a, eam movw a, io movw a, @a movw a, #imm16 movw a, @rwi+disp8 movw a, @rli+disp8 movw dir, a movw addr16, a movw sp, a movw rwi, a movw ear, a movw eam, a movw io, a movw @rwi+disp8, a movw @rli+disp8, a movw rwi, ear movw rwi, eam movw ear, rwi movw eam, rwi movw rwi, #imm16 movw io, #imm16 movw ear, #imm16 movw eam, #imm16 movw al, ah /movw @a, t xchw a, ear xchw a, eam xchw rwi, ear xchw rwi, eam 2 3 1 1 2 2+ 2 2 3 2 3 2 3 1 1 2 2+ 2 2 3 2 2+ 2 2+ 3 4 4 4+ 2 2 2+ 2 2+ 3 4 1 2 2 3+ (a) 3 3 2 5 10 3 4 1 2 2 3+ (a) 3 5 10 3 4+ (a) 4 5+ (a) 2 5 2 4+ (a) 3 4 5+ (a) 7 9+ (a) 0 0 0 1 1 0 0 0 0 1 2 0 0 0 1 1 0 0 1 2 2 1 2 1 1 0 1 0 0 2 0 4 2 (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) 0 0 0 (c) (c) (c) (c) (0) (c) 0 (c) 0 (c) 0 (c) (c) 0 2 (c) 0 2 (c) word (a) ? (dir) word (a) ? (addr16) word (a) ? (sp) word (a) ? (rwi) word (a) ? (ear) word (a) ? (eam) word (a) ? (io) word (a) ? ((a)) word (a) ? imm16 word (a) ? ((rwi) +disp8) word (a) ? ((rli) +disp8) word (dir) ? (a) word (addr16) ? (a) word (sp) ? (a) word (rwi) ? (a) word (ear) ? (a) word (eam) ? (a) word (io) ? (a) word ((rwi) +disp8) ? (a) word ((rli) +disp8) ? (a) word (rwi) ? (ear) word (rwi) ? (eam) word (ear) ? (rwi) word (eam) ? (rwi) word (rwi) ? imm16 word (io) ? imm16 word (ear) ? imm16 word (eam) ? imm16 word ((a)) ? (ah) word (a) ? (ear) word (a) ? (eam) word (rwi) ? (ear) word (rwi) ? (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * C * C * C C C C * * * * * * * * * * * * * * * * * * * * * * * * * C * C * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C movl a, ear movl a, eam movl a, #imm32 movl ear, a movl eam, a 2 2+ 5 2 2+ 4 5+ (a) 3 4 5+ (a) 2 0 0 2 0 0 (d) 0 0 (d) long (a) ? (ear) long (a) ? (eam) long (a) ? imm32 long (ear) ? (a) long (eam) ? (a) C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * C C C C C C C C C C C C C C C
81 mb90640a series table 9 addition and subtraction instructions (byte/word/long word) [42 instructions] note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah i s t n z v c rmw add a,#imm8 add a, dir add a, ear add a, eam add ear, a add eam, a addc a addc a, ear addc a, eam adddc a sub a, #imm8 sub a, dir sub a, ear sub a, eam sub ear, a sub eam, a subc a subc a, ear subc a, eam subdc a 2 2 2 2+ 2 2+ 1 2 2+ 1 2 2 2 2+ 2 2+ 1 2 2+ 1 2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 0 0 1 0 2 0 0 1 0 0 0 0 1 0 2 0 0 1 0 0 0 (b) 0 (b) 0 2 (b) 0 0 (b) 0 0 (b) 0 (b) 0 2 (b) 0 0 (b) 0 byte (a) ? (a) +imm8 byte (a) ? (a) +(dir) byte (a) ? (a) +(ear) byte (a) ? (a) +(eam) byte (ear) ? (ear) + (a) byte (eam) ? (eam) + (a) byte (a) ? (ah) + (al) + (c) byte (a) ? (a) + (ear) + (c) byte (a) ? (a) + (eam) + (c) byte (a) ? (ah) + (al) + (c) (decimal) byte (a) ? (a) Cimm8 byte (a) ? (a) C (dir) byte (a) ? (a) C (ear) byte (a) ? (a) C (eam) byte (ear) ? (ear) C (a) byte (eam) ? (eam) C (a) byte (a) ? (ah) C (al) C (c) byte (a) ? (a) C (ear) C (c) byte (a) ? (a) C (eam) C (c) byte (a) ? (ah) C (al) C (c) (decimal) z z z z C z z z z z z z z z C C z z z z C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C C C C * C C C C C C C C C * C C C C addw a addw a, ear addw a, eam addw a, #imm16 addw ear, a addw eam, a addcw a, ear addcw a, eam subw a subw a, ear subw a, eam subw a, #imm16 subw ear, a subw eam, a subcw a, ear subcw a, eam 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a) 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a) 0 1 0 0 2 0 1 0 0 1 0 0 2 0 1 0 0 0 (c) 0 0 2 (c) 0 (c) 0 0 (c) 0 0 2 (c) 0 (c) word (a) ? (ah) + (al) word (a) ? (a) +(ear) word (a) ? (a) +(eam) word (a) ? (a) +imm16 word (ear) ? (ear) + (a) word (eam) ? (eam) + (a) word (a) ? (a) + (ear) + (c) word (a) ? (a) + (eam) + (c) word (a) ? (ah) C (al) word (a) ? (a) C (ear) word (a) ? (a) C (eam) word (a) ? (a) Cimm16 word (ear) ? (ear) C (a) word (eam) ? (eam) C (a) word (a) ? (a) C (ear) C (c) word (a) ? (a) C (eam) C (c) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C C C C * C C C C C C C * C C addl a, ear addl a, eam addl a, #imm32 subl a, ear subl a, eam subl a, #imm32 2 2+ 5 2 2+ 5 6 7+ (a) 4 6 7+ (a) 4 2 0 0 2 0 0 0 (d) 0 0 (d) 0 long (a) ? (a) + (ear) long (a) ? (a) + (eam) long (a) ? (a) +imm32 long (a) ? (a) C (ear) long (a) ? (a) C (eam) long (a) ? (a) Cimm32 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * C C C C C C
82 mb90640a series table 10 increment and decrement instructions (byte/word/long word) [12 instructions] note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. table 11 compare instructions (byte/word/long word) [11 instructions] note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah i s t n z v c rmw inc ear inc eam dec ear dec eam 2 2+ 2 2+ 2 5+ (a) 3 5+ (a) 2 0 2 0 0 2 (b) 0 2 (b) byte (ear) ? (ear) +1 byte (eam) ? (eam) +1 byte (ear) ? (ear) C1 byte (eam) ? (eam) C1 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C C C * C * incw ear incw eam decw ear decw eam 2 2+ 2 2+ 3 5+ (a) 3 5+ (a) 2 0 2 0 0 2 (c) 0 2 (c) word (ear) ? (ear) +1 word (eam) ? (eam) +1 word (ear) ? (ear) C1 word (eam) ? (eam) C1 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C C C * C * incl ear incl eam decl ear decl eam 2 2+ 2 2+ 7 9+ (a) 7 9+ (a) 4 0 4 0 0 2 (d) 0 2 (d) long (ear) ? (ear) +1 long (eam) ? (eam) +1 long (ear) ? (ear) C1 long (eam) ? (eam) C1 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C C C * C * mnemonic # ~ rg b operation lh ah i s t n z v c rmw cmp a cmp a, ear cmp a, eam cmp a, #imm8 1 2 2+ 2 1 2 3+ (a) 2 0 1 0 0 0 0 (b) 0 byte (ah) C (al) byte (a) ? (ear) byte (a) ? (eam) byte (a) ? imm8 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * C C C C cmpw a cmpw a, ear cmpw a, eam cmpw a, #imm16 1 2 2+ 3 1 2 3+ (a) 2 0 1 0 0 0 0 (c) 0 word (ah) C (al) word (a) ? (ear) word (a) ? (eam) word (a) ? imm16 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * C C C C cmpl a, ear cmpl a, eam cmpl a, #imm32 2 2+ 5 6 7+ (a) 3 2 0 0 0 (d) 0 word (a) ? (ear) word (a) ? (eam) word (a) ? imm32 C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C
83 mb90640a series table 12 multiplication and division instructions (byte/word/long word) [11 instructions] *1: 3 when the result is zero, 7 when an overflow occurs, and 15 normally. *2: 4 when the result is zero, 8 when an overflow occurs, and 16 normally. *3: 6 + (a) when the result is zero, 9 + (a) when an overflow occurs, and 19 + (a) normally. *4: 4 when the result is zero, 7 when an overflow occurs, and 22 normally. *5: 6 + (a) when the result is zero, 8 + (a) when an overflow occurs, and 26 + (a) normally. *6: (b) when the result is zero or when an overflow occurs, and 2 (b) normally. *7: (c) when the result is zero or when an overflow occurs, and 2 (c) normally. *8: 3 when byte (ah) is zero, and 7 when byte (ah) is not zero. *9: 4 when byte (ear) is zero, and 8 when byte (ear) is not zero. *10: 5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0. *11: 3 when word (ah) is zero, and 11 when word (ah) is not zero. *12: 4 when word (ear) is zero, and 12 when word (ear) is not zero. *13: 5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero. note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah i s t n z v c rmw divu a divu a, ear divu a, eam divuw a, ear divuw a, eam mulu a mulu a, ear mulu a, eam muluw a muluw a, ear muluw a, eam 1 2 2+ 2 2+ 1 2 2+ 1 2 2+ *1 * 2 * 3 * 4 * 5 * 8 * 9 * 10 * 11 * 12 * 13 0 1 0 1 0 0 1 0 0 1 0 0 0 * 6 0 * 7 0 0 (b) 0 0 (c) word (ah) /byte (al) quotient ? byte (al) remainder ? byte (ah) word (a)/byte (ear) quotient ? byte (a) remainder ? byte (ear) word (a)/byte (eam) quotient ? byte (a) remainder ? byte (eam) long (a)/word (ear) quotient ? word (a) remainder ? word (ear) long (a)/word (eam) quotient ? word (a) remainder ? word (eam) byte (ah) *byte (al) ? word (a) byte (a) *byte (ear) ? word (a) byte (a) *byte (eam) ? word (a) word (ah) *word (al) ? long (a) word (a) *word (ear) ? long (a) word (a) *word (eam) ? long (a) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * C C C C C C * * * * * C C C C C C C C C C C C C C C C C
84 mb90640a series table 13 logical 1 instructions (byte/word) [39 instructions ] note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah i s t n z v c rmw and a, #imm8 and a, ear and a, eam and ear, a and eam, a or a, #imm8 or a, ear or a, eam or ear, a or eam, a xor a, #imm8 xor a, ear xor a, eam xor ear, a xor eam, a not a not ear not eam 2 2 2+ 2 2+ 2 2 2+ 2 2+ 2 2 2+ 2 2+ 1 2 2+ 2 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 5+ (a) 2 3 5+ (a) 0 1 0 2 0 0 1 0 2 0 0 1 0 2 0 0 2 0 0 0 (b) 0 2 (b) 0 0 (b) 0 2 (b) 0 0 (b) 0 2 (b) 0 0 2 (b) byte (a) ? (a) and imm8 byte (a) ? (a) and (ear) byte (a) ? (a) and (eam) byte (ear) ? (ear) and (a) byte (eam) ? (eam) and (a) byte (a) ? (a) or imm8 byte (a) ? (a) or (ear) byte (a) ? (a) or (eam) byte (ear) ? (ear) or (a) byte (eam) ? (eam) or (a) byte (a) ? (a) xor imm8 byte (a) ? (a) xor (ear) byte (a) ? (a) xor (eam) byte (ear) ? (ear) xor (a) byte (eam) ? (eam) xor (a) byte (a) ? not (a) byte (ear) ? not (ear) byte (eam) ? not (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * r r r r r r r r r r r r r r r r r r C C C C C C C C C C C C C C C C C C C C C C * C C C C * C C C C * C C * andw a andw a, #imm16 andw a, ear andw a, eam andw ear, a andw eam, a orw a orw a, #imm16 orw a, ear orw a, eam orw ear, a orw eam, a xorw a xorw a, #imm16 xorw a, ear xorw a, eam xorw ear, a xorw eam, a notw a notw ear notw eam 1 3 2 2+ 2 2+ 1 3 2 2+ 2 2+ 1 3 2 2+ 2 2+ 1 2 2+ 2 2 3 4+ (a) 3 5+ (a) 2 2 3 4+ (a) 3 5+ (a) 2 2 3 4+ (a) 3 5+ (a) 2 3 5+ (a) 0 0 1 0 2 0 0 0 1 0 2 0 0 0 1 0 2 0 0 2 0 0 0 0 (c) 0 2 (c) 0 0 0 (c) 0 2 (c) 0 0 0 (c) 0 2 (c) 0 0 2 (c) word (a) ? (ah) and (a) word (a) ? (a) and imm16 word (a) ? (a) and (ear) word (a) ? (a) and (eam) word (ear) ? (ear) and (a) word (eam) ? (eam) and (a) word (a) ? (ah) or (a) word (a) ? (a) or imm16 word (a) ? (a) or (ear) word (a) ? (a) or (eam) word (ear) ? (ear) or (a) word (eam) ? (eam) or (a) word (a) ? (ah) xor (a) word (a) ? (a) xor imm16 word (a) ? (a) xor (ear) word (a) ? (a) xor (eam) word (ear) ? (ear) xor (a) word (eam) ? (eam) xor (a) word (a) ? not (a) word (ear) ? not (ear) word (eam) ? not (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * r r r r r r r r r r r r r r r r r r r r r C C C C C C C C C C C C C C C C C C C C C C C C C C * C C C C C * C C C C C * C C *
85 mb90640a series table 14 logical 2 instructions (long word) [6 instructions] table 15 sign inversion instructions (byte/word) [6 instructions] table 16 normalize instruction (long word) [1 instruction] *1: 4 when the contents of the accumulator are all zeroes, 6 + (r0) in all other cases (shift count). note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah i s t n z v c rmw andl a, ear andl a, eam orl a, ear orl a, eam xorl a, ea xorl a, eam 2 2+ 2 2+ 2 2+ 6 7+ (a) 6 7+ (a) 6 7+ (a) 2 0 2 0 2 0 0 (d) 0 (d) 0 (d) long (a) ? (a) and (ear) long (a) ? (a) and (eam) long (a) ? (a) or (ear) long (a) ? (a) or (eam) long (a) ? (a) xor (ear) long (a) ? (a) xor (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * r r r r r r C C C C C C C C C C C C mnemonic # ~ rg b operation lh ah i s t n z v c rmw neg a neg ear neg eam 1 2 2+ 2 3 5+ (a) 0 2 0 0 0 2 (b) byte (a) ? 0 C (a) byte (ear) ? 0 C (ear) byte (eam) ? 0 C (eam) x C C C C C C C C C C C C C C * * * * * * * * * * * * C C * negw a negw ear negw eam 1 2 2+ 2 3 5+ (a) 0 2 0 0 0 2 (c) word (a) ? 0 C (a) word (ear) ? 0 C (ear) word (eam) ? 0 C (eam) C C C C C C C C C C C C C C C * * * * * * * * * * * * C C * mnemonic # ~ rg b operation lh ah i s t n z v c rmw nrml a, r0 2 * 1 10 long (a) ? shift until first digit is 1 byte (r0) ? current shift count CCCCCC*CC C
86 mb90640a series table 17 shift instructions (byte/word/long word) [18 instructions] *1: 6 when r0 is 0, 5 + (r0) in all other cases. *2: 6 when r0 is 0, 6 + (r0) in all other cases. note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah i s t n z v c rmw rorc a rolc a rorc ear rorc eam rolc ear rolc eam asr a, r0 lsr a, r0 lsl a, r0 2 2 2 2+ 2 2+ 2 2 2 2 2 3 5+ (a) 3 5+ (a) * 1 * 1 * 1 0 0 2 0 2 0 1 1 1 0 0 0 2 (b) 0 2 (b) 0 0 0 byte (a) ? right rotation with carry byte (a) ? left rotation with carry byte (ear) ? right rotation with carry byte (eam) ? right rotation with carry byte (ear) ? left rotation with carry byte (eam) ? left rotation with carry byte (a) ? arithmetic right barrel shift (a, r0) byte (a) ? logical right barrel shift (a, r0) byte (a) ? logical left barrel shift (a, r0) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * C * * * * * * * * * * * * * * * * * * C C C C C C C C C * * * * * * * * * C C C * C * C C C asrw a lsrw a/shrw a lslw a/shlw a asrw a, r0 lsrw a, r0 lslw a, r0 1 1 1 2 2 2 2 2 2 * 1 * 1 * 1 0 0 0 1 1 1 0 0 0 0 0 0 word (a) ? arithmetic right shift (a, 1 bit) word (a) ? logical right shift (a, 1 bit) word (a) ? logical left shift (a, 1 bit) word (a) ? arithmetic right barrel shift (a, r0) word (a) ? logical right barrel shift (a, r0) word (a) ? logical left barrel shift (a, r0) C C C C C C C C C C C C C C C C C C C C C C C C * * C * * C * r * * * * * * * * * * C C C C C C * * * * * * C C C C C C asrl a, r0 lsrl a, r0 lsll a, r0 2 2 2 * 2 * 2 * 2 1 1 1 0 0 0 long (a) ? arithmetic right shift (a, r0) long (a) ? logical right barrel shift (a, r0) long (a) ? logical left barrel shift (a, r0) C C C C C C C C C C C C * * C * * * * * * C C C * * * C C C
87 mb90640a series table 18 branch 1 instructions [31 instructions] *1: 4 when branching, 3 when not branching. *2: (b) + 3 (c) *3: read (word) branch address. *4: w: save (word) to stack; r: read (word) branch address. *5: save (word) to stack. *6: w: save (long word) to w stack; r: read (long word) r branch address. *7: save (long word) to stack. note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg boperation lh ah i s t n z v c rmw bz/beq rel bnz/bne rel bc/blo rel bnc/bhs rel bn rel bp rel bv rel bnv rel bt rel bnt rel blt rel bge rel ble rel bgt rel bls rel bhi rel bra rel jmp @a jmp addr16 jmp @ear jmp @eam jmpp @ear * 3 jmpp @eam * 3 jmpp addr24 call @ear * 4 call @eam * 4 call addr16 * 5 callv #vct4 * 5 callp @ear * 6 callp @eam * 6 callp addr24 * 7 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 3 2 2+ 2 2+ 4 2 2+ 3 1 2 2+ 4 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 2 3 3 4+ (a) 5 6+ (a) 4 6 7+ (a) 6 7 10 11+ (a) 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 0 1 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) 0 (d) 0 (c) 2 (c) (c) 2 (c) 2 (c) * 2 2 (c) branch when (z) = 1 branch when (z) = 0 branch when (c) = 1 branch when (c) = 0 branch when (n) = 1 branch when (n) = 0 branch when (v) = 1 branch when (v) = 0 branch when (t) = 1 branch when (t) = 0 branch when (v) xor (n) = 1 branch when (v) xor (n) = 0 branch when ((v) xor (n)) or (z) = 1 branch when ((v) xor (n)) or (z) = 0 branch when (c) or (z) = 1 branch when (c) or (z) = 0 branch unconditionally word (pc) ? (a) word (pc) ? addr16 word (pc) ? (ear) word (pc) ? (eam) word (pc) ? (ear), (pcb) ? (ear +2) word (pc) ? (eam), (pcb) ? (eam +2) word (pc) ? ad24 0 to 15, (pcb) ? ad24 16 to 23 word (pc) ? (ear) word (pc) ? (eam) word (pc) ? addr16 vector call instruction word (pc) ? (ear) 0 to 15 (pcb) ? (ear) 16 to 23 word (pc) ? (eam) 0 to 15 (pcb) ? (eam) 16 to 23 word (pc) ? addr0 to 15, (pcb) ? addr16 to 23 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
88 mb90640a series table 19 branch 2 instructions [19 instructions] *1: 5 when branching, 4 when not branching *2: 13 when branching, 12 when not branching *3: 7 + (a) when branching, 6 + (a) when not branching *4: 8 when branching, 7 when not branching *5: 7 when branching, 6 when not branching *6: 8 + (a) when branching, 7 + (a) when not branching *7: retrieve (word) from stack *8: retrieve (long word) from stack *9: in the cbne/cwbne instruction, do not use the rwj+ addressing mode. note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah i s t n z v c rmw cbne a, #imm8, rel cwbne a, #imm16, rel cbne ear, #imm8, rel cbne eam, #imm8, rel* 9 cwbne ear, #imm16, rel cwbne eam, #imm16, rel* 9 dbnz ear, rel dbnz eam, rel dwbnz ear, rel dwbnz eam, rel int #vct8 int addr16 intp addr24 int9 reti link #local8 unlink ret * 7 retp * 8 3 4 4 4+ 5 5+ 3 3+ 3 3+ 2 3 4 1 1 2 1 1 1 * 1 * 1 * 2 * 3 * 4 * 3 * 5 * 6 * 5 * 6 20 16 17 20 15 6 5 4 6 0 0 1 0 1 0 2 2 2 2 0 0 0 0 0 0 0 0 0 0 0 0 (b) 0 (c) 0 2 (b) 0 2 (c) 8 (c) 6 (c) 6 (c) 8 (c) 6 (c) (c) (c) (c) (d) branch when byte (a) 1 imm8 branch when word (a) 1 imm16 branch when byte (ear) 1 imm8 branch when byte (eam) 1 imm8 branch when word (ear) 1 imm16 branch when word (eam) 1 imm16 branch when byte (ear) = (ear) C 1, and (ear) 1 0 branch when byte (eam) = (eam) C 1, and (eam) 1 0 branch when word (ear) = (ear) C 1, and (ear) 1 0 branch when word (eam) = (eam) C 1, and (eam) 1 0 software interrupt software interrupt software interrupt software interrupt return from interrupt at constant entry, save old frame pointer to stack, set new frame pointer, and allocate local pointer area at constant entry, retrieve old frame pointer from stack. return from subroutine return from subroutine C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C r r r r * C C C C C C C C C C C C C C s s s s * C C C C C C C C C C C C C C C C C C * C C C C * * * * * * * * * * C C C C * C C C C * * * * * * * * * * C C C C * C C C C * * * * * * * * * * C C C C * C C C C * * * * * * C C C C C C C C * C C C C C C C C C C C * C * C C C C C C C C C
89 mb90640a series table 20 other control instructions (byte/word/long word) [36 instructions] *1: pcb, adb, ssb, usb, and spb : 1 state dtb, dpr : 2 states *2: 7 + 3 (pop count) + 2 (last register number to be popped), 7 when rlst = 0 (no transfer register) *3: 29 + (push count) C 3 (last register number to be pushed), 8 when rlst = 0 (no transfer register) *4: pop count (c), or push count (c) *5: pop count or push count. note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah i s t n z v c rmw pushw a pushw ah pushw ps pushw rlst popw a popw ah popw ps popw rlst jctx @a and ccr, #imm8 or ccr, #imm8 mov rp, #imm8 mov ilm, #imm8 movea rwi, ear movea rwi, eam movea a, ear movea a, eam addsp #imm8 addsp #imm16 mov a, brgl mov brg2, a nop adb dtb pcb spb ncc cmr 1 1 1 2 1 1 1 2 1 2 2 2 2 2 2+ 2 2+ 2 3 2 2 1 1 1 1 1 1 1 4 4 4 * 3 3 3 4 * 2 14 3 3 2 2 3 2+ (a) 1 1+ (a) 3 3 * 1 1 1 1 1 1 1 1 1 0 0 0 * 5 0 0 0 * 5 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) (c) (c) * 4 (c) (c) (c) * 4 6 (c) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 word (sp) ? (sp) C2, ((sp)) ? (a) word (sp) ? (sp) C2, ((sp)) ? (ah) word (sp) ? (sp) C2, ((sp)) ? (ps) (sp) ? (sp) C2n, ((sp)) ? (rlst) word (a) ? ((sp)), (sp) ? ( sp) +2 word (ah) ? ((sp)), (sp) ? ( sp) +2 word (ps) ? ((sp)), (sp) ? ( sp) +2 (rlst) ? ((sp)), (sp) ? (sp) +2n context switch instruction byte (ccr) ? (ccr) and imm8 byte (ccr) ? (ccr) or imm8 byte (rp) ? imm8 byte (ilm) ? imm8 word (rwi) ? ear word (rwi) ? eam word (a) ? ear word (a) ? eam word (sp) ? (sp) +ext (imm8) word (sp) ? (sp) +imm16 byte (a) ? (brgl) byte (brg2) ? (a) no operation prefix code for accessing ad space prefix code for accessing dt space prefix code for accessing pc space prefix code for accessing sp space prefix code for no flag change prefix code for common register bank C C C C C C C C C C C C C C C C C C C z C C C C C C C C C C C C * C C C C C C C C C C * * C C * C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C * * C C C C C C C C C C C C C * C * * * C C C C C C C C * * C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C
90 mb90640a series table 21 bit manipulation instructions [21 instructions] *1: 8 when branching, 7 when not branching *2: 7 when branching, 6 when not branching *3: 10 when condition is satisfied, 9 when not satisfied *4: undefined count *5: until condition is satisfied note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg b operation lh ah i s t n z v c rmw movb a, dir:bp movb a, addr16:bp movb a, io:bp movb dir:bp, a movb addr16:bp, a movb io:bp, a setb dir:bp setb addr16:bp setb io:bp clrb dir:bp clrb addr16:bp clrb io:bp bbc dir:bp, rel bbc addr16:bp, rel bbc io:bp, rel bbs dir:bp, rel bbs addr16:bp, rel bbs io:bp, rel sbbs addr16:bp, rel wbts io:bp wbtc io:bp 3 4 3 3 4 3 3 4 3 3 4 3 4 5 4 4 5 4 5 3 3 5 5 4 7 7 6 7 7 7 7 7 7 * 1 * 1 * 2 * 1 * 1 * 2 * 3 * 4 * 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (b) (b) (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) (b) (b) (b) (b) (b) (b) 2 (b) * 5 * 5 byte (a) ? (dir:bp) b byte (a) ? (addr16:bp) b byte (a) ? (io:bp) b bit (dir:bp) b ? (a) bit (addr16:bp) b ? (a) bit (io:bp) b ? (a) bit (dir:bp) b ? 1 bit (addr16:bp) b ? 1 bit (io:bp) b ? 1 bit (dir:bp) b ? 0 bit (addr16:bp) b ? 0 bit (io:bp) b ? 0 branch when (dir:bp) b = 0 branch when (addr16:bp) b = 0 branch when (io:bp) b = 0 branch when (dir:bp) b = 1 branch when (addr16:bp) b = 1 branch when (io:bp) b = 1 branch when (addr16:bp) b = 1, bit = 1 wait until (io:bp) b = 1 wait until (io:bp) b = 0 z z z C C C C C C C C C C C C C C C C C C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * C C C C C C C C C C C C C C C * * * * * * C C C C C C * * * * * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * C C C C C C * C C
91 mb90640a series table 22 accumulator manipulation instructions (byte/word) [6 instructions] table 23 string instructions [10 instructions] m: rw0 value (counter value) n: loop count *1: 5 when rw0 is 0, 4 + 7 (rw0) for count out, and 7 n + 5 when match occurs *2: 5 when rw0 is 0, 4 + 8 (rw0) in any other case *3: (b) (rw0) + (b) (rw0) when accessing different areas for the source and destination, calculate (b) separately for each. *4: (b) n *5: 2 (rw0) *6: (c) (rw0) + (c) (rw0) when accessing different areas for the source and destination, calculate (c) separately for each. *7: (c) n *8: 2 (rw0) note: for an explanation of (a) to (d), refer to table 4, number of execution cycles for each type of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ rg boperation lh ah i s t n z v c rmw swap swapw/xchw al, ah ext extw zext zextw 1 1 1 1 1 1 3 2 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 byte (a) 0 to 7 ? (a) 8 to 15 word (ah) ? (al) byte sign extension word sign extension byte zero extension word zero extension C C x C z C C * C x C z C C C C C C C C C C C C C C C C C C C C * * r r C C * * * * C C C C C C C C C C C C C C C C C C mnemonic # ~ rg b operation lh ah i s t n z v c rmw movs/movsi movsd sceq/sceqi sceqd fisl/filsi 2 2 2 2 2 * 2 * 2 * 1 * 1 6m +6 * 5 * 5 * 5 * 5 * 5 * 3 * 3 * 4 * 4 * 3 byte transfer @ah+ ? @al+, counter = rw0 byte transfer @ahC ? @alC, counter = rw0 byte retrieval (@ah+) C al, counter = rw0 byte retrieval (@ahC) C al, counter = rw0 byte filling @ah+ ? al, counter = rw0 C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * C C * * * C C * * C C C * * C C C C C C movsw/movswi movswd scweq/scweqi scweqd filsw/filswi 2 2 2 2 2 * 2 * 2 * 1 * 1 6m +6 * 8 * 8 * 8 * 8 * 8 * 6 * 6 * 7 * 7 * 6 word transfer @ah+ ? @al+, counter = rw0 word transfer @ahC ? @alC, counter = rw0 word retrieval (@ah+) C al, counter = rw0 word retrieval (@ahC) C al, counter = rw0 word filling @ah+ ? al, counter = rw0 C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * C C * * * C C * * C C C * * C C C C C C
92 mb90640a series n ordering information part number package remarks MB90641Apfv mb90p641apfv 100-pin plastic lqfp (fpt-100p-m05) MB90641Apf mb90p641apf 100-pin plastic qfp (fpt-100p-m06)
93 mb90640a series n package dimensions (.031.008) 0.800.20 lead no. (.012.004) 0.300.10 0.65(.0256)typ 0.30(.012) 0.25(.010) 100 81 80 51 50 31 30 1 22.300.40(.878.016) 18.85(.742)ref m 0.13(.005) (.705.016) (.551.008) 14.000.20 17.900.40 20.000.20(.787.008) 23.900.40(.941.016) index 0.150.05(.006.002) (stand off) 0.05(.002)min 3.35(.132)max (.642.016) 16.300.40 ref 12.35(.486) details of "b" part 0 10 details of "a" part 0.18(.007)max 0.53(.021)max 0.10(.004) "b" "a" 1994 fujitsu limited f100008-3c-2 c (mounting height) c 1995 fujitsu limited f100007s-2c-3 details of "b" part 16.000.20(.630.008)sq 14.000.10(.551.004)sq 0.50(.0197)typ .007 ?.001 +.003 ?0.03 +0.08 0.18 index 0.10(.004) 0.08(.003) m .059 ?.004 +.008 ?0.10 +0.20 1.50 .005 ?.001 +.002 ?0.02 +0.05 0.127 15.00 12.00 (.472) ref (.591) nom "b" "a" 25 26 1 100 75 51 50 76 0.500.20(.020.008) details of "a" part 0.40(.016)max 0.15(.006)max 0.15(.006) 0.15(.006) 0.100.10 (.004.004) (stand off) 0~10? lead no. (mounting height) dimensions in mm (inches) dimensions in mm (inches) 100-pin plastic qfp (fpt-100p-m06) 100-pin plastic lqfp (fpt-100p-m05)
94 mb90640a series memo
95 mb90640a series memo
96 mb90640a series fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-8588, japan tel: (044) 754-3763 fax: (044) 754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, usa tel: (408) 922-9000 fax: (408) 922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: (800) 866-8608 fax: (408) 922-9179 http://www.fujitsumicro.com/ europe fujitsu mikroelektronik gmbh am siebenstein 6-10 d-63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 http://www.fujitsu-ede.com/ asia pacific fujitsu microelectronics asia pte ltd #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 http://www.fmap.com.sg/ f9803 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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